Embedded Hardware: Know It All (eBook)

Front Cover 1
Embedded Hardware 4
Copyright Page 5
Contents 6
About the Authors 14
Chapter 1 Embedded Hardware Basics 18
1.1 Lesson One on Hardware: Reading Schematics 18
1.2 The Embedded Board and the von Neumann Model 22
1.3 Powering the Hardware 26
1.3.1 A Quick Comment on Analog Vs. Digital Signals 27
1.4 Basic Electronics 29
1.4.1 DC Circuits 29
1.4.2 AC Circuits 38
1.4.3 Active Devices 45
1.5 Putting It Together: A Power Supply 49
1.5.1 The Scope 52
1.5.2 Controls 52
1.5.3 Probes 55
Endnotes 58
Chapter 2 Logic Circuits 60
2.1 Coding 60
2.1.1 BCD 63
2.2 Combinatorial Logic 64
2.2.1 NOT Gate 64
2.2.2 AND and NAND Gates 65
2.2.3 OR and NOR Gates 66
2.2.4 XOR 67
2.2.5 Circuits 67
2.2.6 Tristate Devices 70
2.3 Sequential Logic 70
2.3.1 Logic Wrap-Up 74
2.4 Putting It All Together: The Integrated Circuit 75
Endnotes 78
Chapter 3 Embedded Processors 80
3.1 Introduction 80
3.2 ISA Architecture Models 82
3.2.1 Operations 82
3.2.2 Operands 85
3.2.3 Storage 86
3.2.4 Addressing Modes 88
3.2.5 Interrupts and Exception Handling 89
3.2.6 Application-Specific ISA Models 89
3.2.7 General-Purpose ISA Models 91
3.2.8 Instruction-Level Parallelism ISA Models 93
3.3 Internal Processor Design 95
3.3.1 Central Processing Unit (CPU) 99
3.3.2 On-Chip Memory 116
3.3.3 Processor Input/Output (I/O) 130
3.3.4 Processor Buses 147
3.4 Processor Performance 148
3.4.1 Benchmarks 150
Endnotes 150
Chapter 4 Embedded Board Buses and I/O 154
4.1 Board I/O 154
4.2 Managing Data: Serial vs. Parallel I/O 157
4.2.1 Serial I/O Example 1: Networking and Communications: RS-232 161
4.2.2 Example: Motorola/Freescale MPC823 FADS Board RS-232 System Model 163
4.2.3 Serial I/O Example 2: Networking and Communications: IEEE 802.11 Wireless LAN 165
4.2.4 Parallel I/O 170
4.2.5 Parallel I/O Example 3: "Parallel" Output and Graphics I/O 170
4.2.6 Parallel and Serial I/O Example 4: Networking and Communications—Ethernet 173
4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board Ethernet System Model 175
4.2.8 Example 2: Net Silicon ARM7 (6127001) Development Board Ethernet System Model 177
4.2.9 Example 3: Adastra Neptune x86 Board Ethernet System Model 178
4.3 Interfacing the I/O Components 178
4.3.1 Interfacing the I/O Device with the Embedded Board 179
4.3.2 Interfacing an I/O Controller and the Master CPU 181
4.4 I/O and Performance 182
4.5 Board Buses 183
4.6 Bus Arbitration and Timing 185
4.6.1 Nonexpandable Bus: I[sup(2)]C Bus Example 191
4.6.2 PCI (Peripheral Component Interconnect) Bus Example: Expandable 192
4.7 Integrating the Bus with Other Board Components 196
4.8 Bus Performance 197
Chapter 5 Memory Systems 200
5.1 Introduction 200
5.2 Memory Spaces 200
5.2.1 L1 Instruction Memory 203
5.2.2 Using L1 Instruction Memory for Data Placement 203
5.2.3 L1 Data Memory 204
5.3 Cache Overview 204
5.3.1 What Is Cache? 205
5.3.2 Direct-Mapped Cache 207
5.3.3 Fully Associative Cache 207
5.3.4 N-Way Set-Associative Cache 208
5.3.5 More Cache Details 208
5.3.6 Write-Through and Write-Back Data Cache 210
5.4 External Memory 212
5.4.1 Synchronous Memory 212
5.4.2 Asynchronous Memory 220
5.4.3 Nonvolatile Memories 223
5.5 Direct Memory Access 231
5.5.1 DMA Controller Overview 232
5.5.2 More on the DMA Controller 233
5.5.3 Programming the DMA Controller 235
5.5.4 DMA Classifications 245
5.5.5 Register-Based DMA 245
5.5.6 Descriptor-Based DMA 248
5.5.7 Advanced DMA Features 251
Endnotes 253
Chapter 6 Timing Analysis in Embedded Systems 256
6.1 Introduction 256
6.2 Timing Diagram Notation Conventions 256
6.2.1 Rise and Fall Times 258
6.2.2 Propagation Delays 258
6.2.3 Setup and Hold Time 258
6.2.4 Tri-State Bus Interfacing 260
6.2.5 Pulse Width and Clock Frequency 261
6.3 Fan-Out and Loading Analysis: DC and AC 261
6.3.1 Calculating Wiring Capacitance 264
6.3.2 Fan-Out When CMOS Drives LSTTL 266
6.3.3 Transmission-Line Effects 268
6.3.4 Ground Bounce 270
6.4 Logic Family IC Characteristics and Interfacing 272
6.4.1 Interfacing TTL Compatible Signals to 5 V CMOS 275
6.5 Design Example: Noise Margin Analysis Spreadsheet 278
6.6 Worst-Case Timing Analysis Example 287
Endnotes 289
Chapter 7 Choosing a Microcontroller and Other Design Decisions 290
7.1 Introduction 290
7.2 Choosing the Right Core 293
7.3 Building Custom Peripherals with FPGAs 298
7.4 Whose Development Hardware to Use—Chicken or Egg? 299
7.5 Recommended Laboratory Equipment 302
7.6 Development Toolchains 303
7.7 Free Embedded Operating Systems 306
7.8 GNU and You: How Using "Free" Software Affects Your Product 312
Chapter 8 The Essence of Microcontroller Networking: RS-232 318
8.1 Introduction 318
8.2 Some History 320
8.3 RS-232 Standard Operating Procedure 322
8.4 RS-232 Voltage Conversion Considerations 325
8.5 Implementing RS-232 with a Microcontroller 327
8.5.1 Basic RS-232 Hardware 327
8.5.2 Building a Simple Microcontroller RS-232 Transceiver 330
8.6 Writing RS-232 Microcontroller Routines in BASIC 350
8.7 Building Some RS-232 Communications Hardware 356
8.7.1 A Few More BASIC RS-232 Instructions 356
8.8 I[sup(2)]C: The Other Serial Protocol 359
8.8.1 Why Use I[sup(2)]C? 360
8.8.2 The I[sup(2)]C Bus 361
8.8.3 I[sup(2)]C ACKS and NAKS 364
8.8.4 More on Arbitration and Clock Synchronization 364
8.8.5 I[sup(2)]C Addressing 368
8.8.6 Some I[sup(2)]C Firmware 369
8.8.7 The AVR Master I[sup(2)]C Code 369
8.8.8 The AVR I[sup(2)]C Master-Receiver Mode Code 375
8.8.9 The PIC I[sup(2)]C Slave-Transmitter Mode Code 376
8.8.10 The AVR-to-PIC I[sup(2)]C Communications Ball 382
8.9 Communication Options 395
8.9.1 The Serial Peripheral Interface Port 395
8.9.2 The Controller Area Network 397
8.9.3 Acceptance Filters 403
Endnote 404
Chapter 9 Interfacing to Sensors and Actuators 406
9.1 Introduction 406
9.2 Digital Interfacing 406
9.2.1 Mixing 3.3 and 5 V Devices 406
9.2.2 Protecting Digital Inputs 409
9.2.3 Expanding Digital Inputs 415
9.2.4 Expanding Digital Outputs 419
9.3 High-Current Outputs 421
9.3.1 BJT-Based Drivers 422
9.3.2 MOSFETs 426
9.3.3 Electromechanical Relays 428
9.3.4 Solid-State Relays 434
9.4 CPLDs and FPGAs 435
9.5 Analog Interfacing: An Overview 437
9.5.1 ADCs 437
9.5.2 Project 1: Characterizing an Analog Channel 438
9.6 Conclusion 451
Endnote 452
Chapter 10 Other Useful Hardware Design Tips and Techniques 454
10.1 Introduction 454
10.2 Diagnostics 454
10.3 Connecting Tools 455
10.4 Other Thoughts 456
10.5 Construction Methods 457
10.5.1 Power and Ground Planes 458
10.5.2 Ground Problems 458
10.6 Electromagnetic Compatibility 459
10.7 Electrostatic Discharge Effects 459
10.7.1 Fault Tolerance 460
10.8 Hardware Development Tools 461
10.8.1 Instrumentation Issues 462
10.9 Software Development Tools 462
10.10 Other Specialized Design Considerations 463
10.10.1 Thermal Analysis and Design 463
10.10.2 Battery-Powered System Design Considerations 464
10.11 Processor Performance Metrics 465
10.11.1 IPS 465
10.11.2 OPS 465
10.11.3 Benchmarks 466
Appendix A: Schematic Symbols 468
Appendix B: Acronyms and Abbreviations 476
Appendix C: PC Board Design Issues 486
C.1 Introduction 486
C.2 Resistance of Conductors 487
C.3 Voltage Drop in Signal Leads—"Kelvin" Feedback 488
C.4 Signal Return Currents 489
C.5 Grounding in Mixed Analog/Digital Systems 491
C.6 Ground and Power Planes 492
C.7 Double-Sided versus Multilayer Printed Circuit Boards 494
C.8 Multicard Mixed-Signal Systems 495
C.9 Separating Analog and Digital Grounds 496
C.10 Grounding and Decoupling Mixed-Signal ICs with Low Digital Currents 497
C.11 Treat the ADC Digital Outputs with Care 498
C.12 Sampling Clock Considerations 500
C.13 The Origins of the Confusion About Mixed-Signal Grounding: Applying Single-Card Grounding Concepts to Multicard Systems 502
C.14 Summary: Grounding Mixed-Signal Devices with Low Digital Currents in a Multicard System 503
C.15 Summary: Grounding Mixed-Signal Devices with High Digital Currents in a Multicard System 504
C.16 Grounding DSPs with Internal Phase-Locked Loops 504
C.17 Grounding Summary 505
C.18 Some General PC Board Layout Guidelines for Mixed-Signal Systems 506
C.19 Skin Effect 508
C.20 Transmission Lines 510
C.21 Be Careful with Ground Plane Breaks 511
C.22 Ground Isolation Techniques 512
C.23 Static PCB Effects 514
C.24 Sample MINIDIP and SOIC Op Amp PCB Guard Layouts 517
C.25 Dynamic PCB Effects 519
C.26 Stray Capacitance 520
C.27 Capacitive Noise and Faraday Shields 521
C.28 The Floating Shield Problem 523
C.29 Buffering ADCs Against Logic Noise 523
Endnotes 525
Acknowledgments 526
Index 528
A 528
B 528
C 529
D 530
E 531
F 531
G 531
H 532
I 532
J 533
K 533
L 533
M 533
N 534
O 534
P 534
R 535
S 536
T 537
U 537
V 537
W 537
X 537
Z 537