Code Optimization Techniques for Embedded Processors - Rainer Leupers

Code Optimization Techniques for Embedded Processors

Methods, Algorithms, and Tools

(Autor)

Buch | Softcover
216 Seiten
2010 | Softcover reprint of hardcover 1st ed. 2000
Springer-Verlag New York Inc.
978-1-4419-5010-9 (ISBN)
106,99 inkl. MwSt
The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice.
The building blocks of today's and future embedded systems are complex intellectual property components, or cores, many of which are programmable processors. Traditionally, these embedded processors mostly have been pro­ grammed in assembly languages due to efficiency reasons. This implies time­ consuming programming, extensive debugging, and low code portability. The requirements of short time-to-market and dependability of embedded systems are obviously much better met by using high-level language (e.g. C) compil­ ers instead of assembly. However, the use of C compilers frequently incurs a code quality overhead as compared to manually written assembly programs. Due to the need for efficient embedded systems, this overhead must be very low in order to make compilers useful in practice. In turn, this requires new compiler techniques that take the specific constraints in embedded system de­ sign into account. An example are the specialized architectures of recent DSP and multimedia processors, which are not yet sufficiently exploited by existing compilers.

1. Introduction.- 2. Memory Address Computation for DSPS.- 3. Register Allocation for DSP Data Paths.- 4. Instruction Scheduling for Clustered VLIW Processors.- 5. Code Selection for Multimedia Processors.- 6. Performance Optimization with Conditional Instructions.- 7. Function Inlining under Code Size Constraints.- 8. Frontend Issues — The Lance System.- 9. Conclusions.- Appendices.- A— Experimental Result Tables.- B— Example for the LANCE V2.0 IR.- References.- About the Author.

Erscheint lt. Verlag 29.10.2010
Zusatzinfo VIII, 216 p.
Verlagsort New York, NY
Sprache englisch
Maße 155 x 235 mm
Themenwelt Mathematik / Informatik Informatik Netzwerke
Informatik Theorie / Studium Künstliche Intelligenz / Robotik
Informatik Weitere Themen CAD-Programme
Technik Elektrotechnik / Energietechnik
ISBN-10 1-4419-5010-9 / 1441950109
ISBN-13 978-1-4419-5010-9 / 9781441950109
Zustand Neuware
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