ESD Design for Analog Circuits (eBook)

Dr. Vladislav Vashchenko received MS, Engineer-Physicist (1986) followed by “Ph.D. in Physics of Semiconductors” (1990) from Moscow Institute of Physics and Technology for the study of self-organization phenomena in semiconductor structures under breakdown. Since 1984 he was working in reliability department of State Research Institute “Pulsar” (Moscow) occupying positions from the student intern to head of laboratory. In 1997 he was awarded the “Doctor of Science in Microelectronics” degree for the cycle of studies and new solutions of the reliability problems in power GaAs MESFET’s, microwave silicon devices and the developed test methods. In the period 1995-1997 he managed the work on contracts for high reliability components for Russian Space Agency, commercial and military customers. In 2000 he joined Advanced Process Development Group in National Semiconductor Corp. to work on design of the ESD protection solutions for analog products. Currently he is leader and manager of R&D group responsible for ESD development for new processes and products. His current research interests are mainly focused on the power devices, device level reliability, ESD solutions, physical process and device simulation for ESD. His studies are widely presented in major device research forums. He author of 108 U.S. patents and over 80 research and review papers in the fields of reliability and ESD.

Preface 6
This Book and Simulation Software Bundle Project 6
Subject and Purpose of This Book 7
The Book Structure 8
Acknowledgments 11
Contents 13
1 Introduction 19
1.1 Analog and Digital in Prism of ESD Design 19
1.2 Important Definitions 22
1.2.1 ESD Protection Network 22
1.2.2 ESD Clamps 24
1.2.3 Absolute Maximum Limits and Pulsed SOA 25
1.2.4 ESD Pulse Specification 26
1.2.5 Breakdown and Instability 27
DECIMM TM Simulation Examples for Introduction 32
2 Conductivity Modulation in Semiconductor Structures Under Breakdown and Injection 33
2.1 Important Definitions and Limitations 33
2.1.1 Basic Semiconductor Structures 33
2.1.2 Conductivity Modulation and Negative Differential Resistance 35
2.1.3 Spatial Current Instability, Filamentation, and Suppression 36
2.1.4 Snapback Operation 38
2.1.5 Notes to the Methodology of Material Presentation in This Chapter 40
2.2 Avalanche Breakdown in Reverse-Biased pn Structure 41
2.2.1 Analytical Description of the Avalanche Breakdown Phenomenon 42
2.2.2 Numerical Analysis of the Avalanche Breakdown in the p + 0p0n + Structure p + -p-n + structure 44
2.3 Double-AvalancheInjection in pin Structures 48
2.3.1 An Analytical Description of the Effect 48
2.3.2 Numerical Analysis for the p--i--n Diode Structure 49
2.4 AvalancheInjection in Si n + nn + Diode Structure 51
2.4.1 Analytical Approach 52
2.4.2 Simulation Analysis 54
2.5 Conductivity Modulation Instability in npn Diode Structures 55
2.5.1 Conductivity Modulation in a Floating Base Region: Diode Operation Mode 55
2.5.1.1 The Case of Floating Base Breakdown (BVCEO) I B = 0 55
2.5.1.2 Numerical Solution for I B = 0 Case 57
2.6 Conductivity Modulation in the Triode npn Structure 58
2.6.1 The Case of Grounded Base Breakdown Operation U EB = 0 (BVCES) 58
2.6.2 The Floating Emitter Case I E =0 59
2.6.3 Avalanche-Injection in a Common Emitter Circuit: The Case of I B< 0 Regime
2.6.3.1 Numerical Analysis for I B < 0 Case
2.6.4 Avalanche-Injection in the Common Emitter Circuit with Positive Base Current IB> 0
2.6.4.1 Analytical Description of the I B > 0 Case
2.6.4.2 Numerical Analysis of the I B > 0 Case
2.6.5 Avalanche--Injection in the Common Base Circuit 69
2.7 AvalancheInjection in PNP Structures 70
2.8 Double Injection in Si pnpn Structures 71
2.8.1 Equivalent Circuit 71
2.8.2 Simulation of Conductivity Modulation in p--n--p--n Structures 74
2.8.2.1 Floating Base Case 74
2.8.2.2 Connected Base Case 76
2.9 Spatial Current Instability Phenomena in Semiconductor Structures with Negative Differential Resistance 77
2.9.1 Current Filamentation at Avalanche--Injection 78
2.9.2 Current Filamentation Effect in Double-Avalanche--Injection Conductivity Modulation 81
2.9.3 Current Filamentation Effect in the Case of Double Injection 84
2.10 Summary 84
DECIMM TM Simulation Examples DECIMM TM Simulation examples for Chapter 2 86
3 Standard and ESD Devices in Integrated Process Technologies 87
3.1 ESD Specifics in Integrated Process Technology 88
3.1.1 Typical DGO CMOS Process with Extended Voltage Components 88
3.1.1.1 Initial Wafer Material 89
3.1.1.2 Device Isolation 90
3.1.1.3 Deep Nwell isolation 91
3.1.1.4 Well Implants 93
3.1.1.5 Gate Oxide 94
3.1.1.6 Polygate 94
3.1.1.7 Lightly Doped Drain Implants 96
3.1.1.8 Spacer Formation and NPLUS and PPLUS Implants 97
3.1.1.9 Activation and Silicidation 98
3.1.1.10 Contacts and Backend 100
3.1.2 ESD Specific for BCD and BiCMOS Integrated Process Flow 101
3.1.2.1 Generic Process Flow 101
3.1.2.2 Subcollector and Substrate Isolation Regions 102
3.1.2.3 Isolation BCD Process Steps 104
3.1.2.4 Collector and Initial CMOS Regions 104
3.2 Safe Operating Area in ESD Pulse Regime 105
3.2.1 SOA and Current Instability Boundary in Reliability 106
3.2.2 Pulsed SOA for ESD Regimes 108
3.2.2.1 Standard Devices 109
3.2.3 ESD SOA for Typical Devices in BCD Process 110
3.2.3.1 Waveform SOA Measurements 113
3.2.4 Instability Boundary and SOA for ESD devices 114
3.2.5 Physical Limitation of ESD Devices. Spatial Thermal Runaway 116
3.3 Low-Voltage ESD Devices in CMOS Processes 120
3.3.1 Snapback NMOS 121
3.3.1.1 Three-Dimensional Simulation of Current Instability in Snapback NMOS Devices 122
3.3.2 FOX (TFO) ESD device 123
3.3.2.1 Surface NPN 125
3.3.3 LVTSCR and FOXSCR 127
3.3.4 Low-Voltage Avalanche Diodes 129
3.3.4.1 Comparison of the Surface and Buried Avalanche Diodes 130
3.4 ESD Devices in BJT Processes 130
3.4.1 Integrated NPN BJT Devices 132
3.4.2 Bipolar SCR 134
3.5 High-Voltage ESD Devices in BCD and Extended Voltage CMOS Processes 135
3.5.1 LDMOS-SCR and DeMOS-SCR Devices 136
3.5.2 Lateral PNP BJT Devices 139
3.5.3 High-Voltage Avalanche Diodes 144
3.6 Dual Direction Devices 145
3.6.1 Dual-Direction Device Architecture in CMOS Process 146
3.6.1.1 Device-Level Positive and Negative Feedback 147
3.6.2 High-Voltage Dual-Direction Devices 149
3.6.3 Dual Direction ESD Devices Based upon Si--Ge NPN BJT Structure 152
3.6.3.1 Experimental Characteristics of the DD-BJT Clamp 155
3.7 ESD Diodes and Passive Components 157
3.7.1 Forward-Biased ESD Diodes 157
3.7.1.1 CMOS Diodes CMOS diodes 158
3.7.1.2 Gated Diodes Gated diodes 159
3.7.2 Passives 160
3.7.2.1 Saturation Resistors Saturation resistors [ 59 ] 161
3.7.2.2 Thin Film Resistors 164
3.8 Summary 165
DECIMM TM Simulation Examples for Chapter 3 166
Example 3.1 Standard Devices in BCD Process Technology 167
Example 3.2 Typical ESD Devices in 0.5 m BCD Process Technology 168
Example 3.3 Ring Oscillators 171
4 ESD Clamps 173
4.1 Active NMOS Clamp 176
4.2 Low-Voltage Clamps with Internal Blocking Junction Reference or d V /d t Turn-on 179
4.2.1 Snapback NMOS Clamps 179
4.2.1.1 Ground-Referenced Snapback NMOS 179
4.2.1.2 Gate Coupling 179
4.2.1.3 Displacement Current Effect 180
4.2.1.4 Reverse Path Protection 182
4.2.1.5 Isolated Snapback NMOS Isolated Snapback NMOS 182
4.2.1.6 The 40 Rule for Backend 184
4.2.2 Transient-Triggered PMOS Clamp 185
4.2.3 100V FOX Snapback Device FOX Snapback device 187
4.2.4 LVTSCR and FOX-SCR Clamps 189
4.2.5 High Holding Voltage LVTSCR Clamps 190
4.2.5.1 High Holding Voltage Cell Topology 190
4.2.5.2 Clamp-Level High Holding Voltage Using P-Emitter De-biasing 192
4.2.6 Triggering Characteristics Control in SCR Clamps 194
4.2.6.1 Mixed Device-Circuit Concept 195
4.2.6.2 Practical Implementation of the Concept for the Case of 130 nm Process 195
4.2.6.3 Principle of Dual-Base Control Operation 196
4.2.6.4 Pulsed Characterization of Dual-Base Control (DBC) Clamp 198
4.2.6.5 DC Leakage of DBC Clamp 199
4.3 Voltage and Current Reference in ESD Clamp 200
4.3.1 Low-Voltage Clamps in BiCMOS process technology 201
4.3.2 NPN Clamps with Voltage Reference 203
4.4 High-Voltage ESD Devices 206
4.4.1 20 V NPN with Blocking Junction Internal Reference 207
4.4.2 NPN Clamp with External Lateral Avalanche Diode Reference 208
4.4.3 SCR-Based High-Voltage Clamp 208
4.4.4 Lateral LPNP Clamp 208
4.4.5 Mixed Device-Circuit Dual Mode Solutions 209
4.4.5.1 Example of Circuit Design 210
4.5 The Concept of Self-Protection 214
4.5.1 Device-Level Self-Protection 214
4.5.2 Array-Level Protection 216
4.6 ESD Protection of Ultra High Voltage Circuits 218
4.7 Summary 221
DECIMMTM Simulation Examples for Chapter 4 222
Example 4.1 Snapback NMOS Clamp Operation Analysis 222
Example 4.2 LVTSCR ESD Clamps 223
Example 4.3 Two-Stage ESD Protection with Snapback NMOS 224
Example 4.4 High-Voltage NLDMOS-SCR Clamp with High-Side Avalanche Diode Reference 225
Example 4.5 PNP Clamp with Low Side Avalanche Diode Reference 226
Example 4.6 High-Voltage NPN Clamp 227
Example 4.7 Bipolar SCR ESD Clamp 228
Example 4.8 Diode-Triggered SCR ESD Clamp 229
5 ESD Network Design Principles 231
5.1 Rail-Based ESD Protection Network 233
5.1.1 Rail Based and Local ESD Protection 233
5.1.2 Rail-Based ESD Protection Using Snapback Clamps 235
5.1.3 Rail-Based ESD Protection Using Active Clamps 237
5.1.4 Specific of Active Clamp Design in BiCMOS Processes 241
5.1.4.1 Verification by Circuit Simulation 241
5.1.4.2 Experimental Comparison 243
5.1.4.3 Active Clamp Protection in Complementary BiCMOS with Low-Voltage CMOS Components 245
5.1.5 Bipolar Differential Input Protection 250
5.1.6 Bipolar Output Protection 252
5.1.7 CMOS Input and Output Protection 253
5.1.8 Array-Level Consideration 255
5.1.9 Concept of Two-Stage Protection 258
5.1.9.1 CMOS Input CMOS Input 258
5.1.9.2 Diode-Based Compact Two-Stage ESD Protection Circuit 259
5.1.9.3 Two-Stage ESD Protection Circuit for BJT Base 261
5.1.9.4 Two-Stage Network with Snapback NMOS 262
5.2 Local Clamp-Based ESD Protection Network 265
5.2.1 Local ESD Protection 265
5.2.2 Serial Data Line Pin Case Study 266
5.2.3 Erase Pin Protection in EEPROM 268
5.2.4 Local Protection of the Internal Pins 271
5.2.5 Local Protection of the High-Speed I/O pins 274
5.3 ESD Network for Multiple Voltage Domains 276
5.3.1 Multiple Voltage Domains 276
5.3.2 Protection of Multiple Voltage Domains with Single Active Clamp Network 278
5.3.3 Local Bi-directional ESD Protection of Differential Input 279
5.4 ESD Network Simulation with ESD Compact Models 281
5.4.1 Compact Model for Snapback NMOS and PMOS Devices 281
5.4.2 Snapback LVTSCR Model 283
5.4.3 Extended Voltage Snapback Compact Models 283
5.4.4 High-Voltage Open Drain Circuit Analysis 288
5.5 Summary 290
DECIMM TM Simulation Examples for Chapter 5 290
Example 5.1 Active 5 V NMOS Clamp 290
Example 5.2 Active 5 V PMOS Clamp 291
Example 5.3 EEPROM Erase pin Protection 292
Example 5.4 BJT-Based Active Clamps 293
Example 5.5 Stacked Active Clamps for High Voltage Tolerance 295
Example 5.6 Stacked Active Clamps with NPN 296
Example 5.7 Stacked Active Clamps with PNP 297
6 ESD Design for Signal Path Analog 298
6.1 Amplifiers 299
6.1.1 Amplifier Product Families and Specifications 299
6.1.2 ESD Solutions for Amplifiers 305
6.1.3 Bipolar Output High-Voltage Audio Amplifiers 307
6.1.4 Bipolar Output Protection in Low-Voltage Amplifiers 309
6.1.5 Input Protection 310
6.1.6 CMOS Output 312
6.2 Digital-to-Analog and Analog-to-Digital Converters 313
6.2.1 Functional Blocks for High-Speed DAC 314
6.2.1.1 ESD Protection Network 316
6.3 High-Speed Interface IO pins 318
6.3.1 Interface Analog Products 318
6.3.2 Cable Discharge Event Test Procedure for Integrated Circuits 319
6.3.3 ESD Protection of Interface Pins with CDE Requirements 322
6.4 Summary 324
DECIMMTM Simulation Examples for Chapter 6 324
Example 6.1a 6.1c Rail-Based Protection with Active 5 V NMOS Clamp and ESD Diodes 325
Example 6.2 Rail-Based Protection with 5 V Snapback NMOS Clamp and ESD Diodes 327
Example 6.3 Trans Impedance Amplifier 329
Example 6.4 CMOS Output Stage ESD Case 329
Example 6.5 CMOS Open Drain Case 330
Example 6.6 BJT Output Stage Case 331
7 Power Management Circuits ESD Protection 333
7.1 Power Management Products 334
7.1.1 Power Management Products and ESD Challenges 334
7.1.1.1 Market Trends 334
7.1.1.2 ESD Challenges 335
7.1.2 Integrated DC--DC Converters and Controllers 337
7.1.3 Integrated Power Arrays 339
7.1.3.1 Power Losses 339
7.1.3.2 Self-Protection Capability (SPC) of Integrated Power Arrays 344
7.1.3.3 Physical Simulation of DeMOS Power Arrays in ESD Regime 350
7.2 Low-Voltage Power Circuit ESD Cases 354
7.2.1 LV Power Switching Blocks 354
7.2.2 Step-Down DC--DC Converters 356
7.2.3 Local Snapback Protection of LV Switch Pin 359
7.2.3.1 Case Study 359
7.2.3.2 Mixed-Mode Simulation 361
7.3 ESD Protection of Integrated High-Voltage Regulators 363
7.3.1 Asynchronous Integrated Buck Regulator Case 363
7.3.1.1 Functionality and ESD Protection 363
7.3.1.2 Case Study 365
7.3.2 Synchronous Regulators 367
7.3.2.1 HV Power Train Block 367
7.3.2.2 Synchronous Buck Regulator 369
7.4 Controllers 373
7.4.1 Asynchronous Buck-Boost (SEPIC) Controller 375
7.4.2 Synchronous Buck Controller 378
7.5 Light Management Units and LED Drivers 380
7.5.1 Analog LED Technology 380
7.5.2 LED Drivers 382
7.5.3 Light Management Units 383
7.5.3.1 Switch Pin Protection 386
7.5.3.2 Feedback Pin Protection 386
7.5.3.3 LED Driver Protection 387
7.5.3.4 Gate Clamp 388
7.5.3.5 RGB Driver 388
7.5.3.6 Control Pins 389
7.5.3.7 Current Sink Protection 390
7.6 A Few More Case Studies 390
7.6.1 Power Array--ESD Clamp Interaction 390
7.6.2 Nepi--Nepi Transient Latch-Up Scenario 393
7.6.3 CDM Case of the High-Voltage Pin Protection 396
7.7 Summary 399
DECIMMTM Simulation Examples for Chapter 7 403
Example 7.1 Output Stage of Buck DC--DC Voltage Regulator 403
Example 7.2 5--V Boost DC--DC Converter and Transient Latch-Up 404
Example 7.3 High-Voltage Boost Output Stage 405
Example 7.4 100 600 V Boost Output Stage with Vertical DMOS and IGBT 406
Example 7.5 Power Array with Gate Clamp Example 406
Example 7.6 Serial Data Line Pin Case 407
8 System-Level and Discrete Components ESD 410
8.1 System-Level Specifications and Standards 411
8.1.1 Meaning of ESD Robust System 411
8.1.1.1 CE Mark 412
8.1.1.2 Basic EMC Standards 412
8.1.1.3 Automotive Industry Standards 412
8.1.1.4 IC and System-Level Comparison 413
8.1.2 System-Level ESD Pulse and Model 415
8.1.2.1 System-Level ESD Test for ICs 415
8.1.2.2 IEC ESD Pulse Waveforms 415
8.1.2.3 System-Level Test Setup 418
8.1.2.4 Cable Discharge Event (CDE) 419
8.1.3 Transient Latch-up During a System-Level Event 420
8.1.4 System-Level Protection Components 423
8.2 On-Wafer Human Metal Model Measurements 424
8.2.1 On-Wafer HMM Tester and Equivalent Circuit of the Pulse 425
8.2.1.1 Equivalent Circuit for HMM Simulation 426
8.2.2 HMM-HBM Component Correlation 427
8.2.2.1 Diodes Under HMM Stress 429
8.2.2.2 LVTSCR 429
8.2.2.3 High-Voltage ESD Clamps 430
8.3 On-Chip Design for System-Level Pins 431
8.3.1 Examples of Circuits with System-Level Protection 431
8.3.1.1 On-Chip and Suppressor ESD Device Interaction 436
8.4 Hot Swap and Hot Plug-in 437
8.4.1 The Concept of Two-Stage SCR ESD Devices 437
8.5 System-on-Package (SOP) Protection 443
8.6 ESD Robustness of Discrete Components 444
8.6.1 Discrete Components in High Reliability Systems 444
8.6.2 ESD Requirement for Discrete Components 444
8.6.2.1 ESD Effects on Power Transistors 445
8.6.2.2 Statistical Approach for ESD and Reliability Parameters Verification 446
8.6.3 Preliminary Numerical Analysis for Devices with Defects and the Two-Transistor Model 447
8.6.4 Experimental Evaluation of Discrete Components Discrete Components Robustness 451
8.6.4.1 TLP Stress 452
8.6.4.2 ISO System-Level Pulse Test 453
8.6.4.3 Collector--Emitter ISO Test 454
8.6.4.4 Gate--Collector ISO Tests 456
8.7 Summary 457
DECIMM TM Simulation Examples for Chapter 8 458
Example 8.1 System HMM Pulse Simulation 458
Example 8.2 HMM Simulation with PCB Components and TVS 458
Example 8.3 Power Switch 458
References 462
Index 470