Electrical Modeling and Design for 3D System Integration (eBook)

ER-PING LI, PhD, holds an appointment as Chair Professor at Zhejiang University, China, and has also been a principal scientist and director at the Institute of High Performance Computing, Singapore. He is a Fellow of the IEEE and a Fellow of the Electromagnetics Academy. He has received numerous awards and honors in recognition of his professional work from the IEEE and other professional bodies. Dr. Li is a pioneer in the modeling and simulation for signal/power and EMC in integrated circuits and electronic systems packaging. He has chaired or spoken at numerous international conferences and universities, and has also served as editor to several IEEE Transactions.

Foreword xi

Preface xiii

1. Introduction 1

1.1 Introduction of Electronic Package Integration, 1

1.2 Review of Modeling Technologies, 6

1.3 Organization of the Book, 10

2. Macromodeling of Complex Interconnects in 3D Integration 16

2.1 Introduction, 16

2.2 Network Parameters: Impedance, Admittance, and Scattering Matrices, 19

2.3 Rational Function Approximation with Partial Fractions, 25

2.4 Vector Fitting (VF) Method, 29

2.5 Macromodel Synthesis, 41

2.6 Stability, Causality, and Passivity of Macromodel, 48

2.7 Macromodeling Applied to High-Speed Interconnects and Circuits, 79

2.8 Conclusion, 91

3. 2.5D Simulation Method for 3D Integrated Systems 97

3.1 Introduction, 97

3.2 Multiple Scattering Method for Electronic Package Modeling with Open Boundary Problems, 98

3.3 Novel Boundary Modeling Method for Simulation of Finite-Domain Power-Ground Planes, 127

3.4 Numerical Simulations for Finite Structures, 133

3.5 Modeling of 3D Electronic Package Structure, 142

3.6 Conclusion, 182

4. Hybrid Integral Equation Modeling Methods for 3D Integration 185

4.1 Introduction, 185

4.2 2D Integral Equation Equivalent Circuit (IEEC) Method, 186

4.3 3D Hybrid Integral Equation Method, 220

4.4 Conclusion, 238

5. Systematic Microwave Network Analysis for 3D Integrated Systems 241

5.1 Intrinsic Via Circuit Model for Multiple Vias in an Irregular Plate Pair, 242

5.2 Parallel Plane Pair Model, 281

5.3 Cascaded Multiport Network Analysis of Multilayer Structure with Multiple Vias, 305

6. Modeling of Through-Silicon Vias (TSV) in 3D Integration 331

6.1 Introduction, 331

6.2 Equivalent Circuit Model for TSV, 336

6.3 MOS Capacitance Effect of TSV, 351

6.4 Conclusion, 356

References, 358

Index 361