System Specification and Design Languages (eBook)

System Specification and Design Languages 3
Preface 5
Contents 7
Contributors 9
Chapter 1 Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors 13
1.1 Introduction 13
1.2 Interval Property Checking 15
1.2.1 Hardware Models and Property Languages 15
1.3 IPC for Weakly Programmable IP 18
1.4 Configuration and Context-Dependent Constraints 21
1.4.1 Hazard Detection 22
1.5 Completeness 24
1.6 Hardware/Software Compliance 27
1.7 Applications 28
1.8 Conclusion 31
References 31
Chapter 2 Evaluating Debugging Algorithms from a Qualitative Perspective 33
2.1 Introduction 33
2.2 Preliminaries 35
2.2.1 Faults, Bugs, and Errors 35
2.2.2 Computation of CFG and PDG 35
2.2.3 Simulation-Based Debugging 36
2.3 General Idea and Discussion 37
2.3.1 Qualitative Assessment 38
2.3.2 Limits of Quantitative Assessments 38
2.4 Fault Model 39
2.4.1 Programming Faults 40
2.4.1.1 Assignment Fault 40
2.4.1.2 Operation Fault 40
2.4.1.3 Incorrect Data/Port Type 41
2.4.2 Design Faults 42
2.4.2.1 Missing Code 42
2.4.2.2 Extra Code 43
2.4.2.3 Misplaced Code 44
2.4.2.4 Signal Binding Faults 44
2.5 Evaluation: Simulation-Based Debugging 45
2.5.1 Limitations of Quantitative Analysis 46
2.5.2 Qualitative Assessment 46
2.6 Conclusion 47
References 47
Chapter 3 Mapping of Concurrent Object-Oriented Models to Extended Real-Time Task Networks 49
3.1 Introduction 49
3.2 Modelling Approach 51
3.2.1 Executable Model – OSSS Design Methodology 51
3.2.2 Analytical/Formal Model 54
3.3 Mapping 57
3.3.1 Port-Interface Binding 57
3.3.2 Shared Object 58
3.3.3 Task Model 59
3.4 Use-Case 60
3.4.1 Service Call 60
3.4.2 Mutual Exclusion 60
3.4.3 Multiplexer with Priority-Based Scheduling 61
3.5 Conclusion and Future Work 64
References 64
Chapter 4 SystemC-A Modelling of Mixed-Technology Systems with Distributed Behaviour 66
4.1 Introduction 66
4.2 SystemC-A 68
4.2.1 Subsection Heading 68
4.2.1.1 Analogue Components 68
4.2.2 Virtual Build Method 69
4.3 Case Study 1: SystemC-A Modelling of Distributed Lossy Transmission Line 69
4.3.1 Distributed Model of Lossy Microstrip 69
4.3.2 SystemC-A Implementation of Proposed Model 71
4.3.3 Simulation Results 73
4.4 Case Study 2: SystemC-A Modelling of the Distributed Cantilever Beam 73
4.4.1 SystemC-A Implementation of Cantilever Beam 76
4.4.2 Simulation Results 78
4.5 Conclusion 78
References 78
Chapter 5 A Framework for Interactive Refinement of Mixed HW/SW/Analog Systems 81
5.1 Introduction 82
5.2 Related Work 82
5.3 Synchronisation 83
5.3.1 Analogue Events 84
5.3.2 Sampled Signals 84
5.3.3 Pre-Synchronisation 85
5.4 Usability 86
5.4.1 Signal Pool 86
5.4.2 SystemC Proxy Module 90
5.4.3 Graphical Design Entry 91
5.5 Design Example 93
5.5.1 Design Effort 94
5.5.2 Performance and Accuracy 95
5.6 Conclusion 97
References 97
Chapter 6 Bottom-up Verification for CMOS Photonic Linear Heterogeneous System 100
6.1 Introduction 101
6.2 Simulation strategy for heterogeneous cmos photonic system 102
6.3 Model implementation 104
6.3.1 Optical passive devices modeling 104
6.3.2 Modeling difficulties 107
6.3.3 Analysis and solution 107
6.3.4 VPI implementation details 109
6.4 Numerical application 109
6.5 Conclusion 111
References 111
Chapter 7 Towards Abstract Analysis Techniques for Range Based System Simulations 114
7.1 Introduction 115
7.2 Related Work 116
7.3 Semi-Symbolic Simulation Environment 116
7.3.1 Affine Arithmetic 117
7.3.2 SystemC AMS 118
7.3.3 Transistor Level Solver 118
7.4 Enhanced Range Signal Analysis 119
7.4.1 Traditional Fourier Transform 120
7.4.2 Range Based Fourier Transformation 120
7.4.3 Amplitude Frequency Spectrum 122
7.4.4 Phase Frequency Spectrum 123
7.4.5 Applied Range Based Fourier Transform 123
7.4.6 Runtime of Range Based Fourier Transform 124
7.5 Fourier Analysis Demonstration 124
7.6 Conclusion and Future Work 128
References 128
Chapter 8 Modeling Time-Triggered Architecture Based Real-Time Systems Using SystemC 131
8.1 Introduction 131
8.2 Related Work 133
8.3 Background 133
8.3.1 SystemC 133
8.3.2 Time Model 134
8.3.3 Component 134
8.4 Executable Time-Triggered Model (E-TTM) 135
8.4.1 Elements and Relationships 135
8.4.2 Time 137
8.4.3 Execution 137
8.4.4 Communication 138
8.4.5 Model Assumptions 139
8.5 Real-Time Control-System Example 139
8.5.1 System Description 140
8.5.2 System Design 140
8.5.3 Simulation Results 142
8.6 Dependability Assesment Example 143
8.6.1 Design 144
8.6.2 Simulated Fault Injection (SFI) 147
8.7 Conclusion 148
References 148
Chapter 9 Towards the Development of a Set of Transaction Level Models A Feature-Oriented Approach 150
9.1 Introduction 150
9.2 Feature-Oriented Programming 151
9.3 Feature-Oriented TPL Development 153
9.3.1 The Universality of TPL 153
9.3.2 Poor Support of OOP for TPL Development 153
9.3.3 FOP Support for TPL Development 156
9.3.3.1 First Point 156
9.3.3.2 Second Point 157
9.3.3.3 Third Point 157
9.3.4 Feature-Oriented TPL Development Method 158
9.4 Case Study: A Simple SoC 158
9.4.1 Domain Analysis 159
9.4.2 Domain Design 159
9.4.2.1 UT Feature 159
9.4.2.2 Timing Feature 160
9.4.2.3 Intr Feature 162
9.4.2.4 PowerEstimation Feature 162
9.4.3 Domain Implementation, Configuration and Generation 162
9.5 Conclusion 163
References 163
Chapter 10 Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL Framework 164
10.1 Introduction 165
10.2 Requirements and Existing Tools 165
10.2.1 Executable Specification 166
10.2.2 Estimation and Representation of Non-Functional Properties 167
10.2.3 System Simulation Including Non-Functional Properties 168
10.2.4 Integrated Framework 169
10.3 Proposed Concept 170
10.3.1 Executable Specification 171
10.3.1.1 Parallel Application Description 171
10.3.1.2 System Input Stimuli 172
10.3.1.3 User Constrained HW/SW Separation and Mapping 172
10.3.1.4 Architecture/Platform Description 172
10.3.2 Estimation and Model Generation 173
10.3.2.1 Hardware/Software Task Separation 173
10.3.2.2 Hard- and Software Estimation 173
10.3.2.3 Pre-existing IP and Virtual Component Models 175
10.3.2.4 Virtual System Generation 176
10.3.3 Virtual System Simulation 176
10.4 Conclusion 179
References 179
Chapter 11 Towards Accurate Source-Level Annotation of Low-Level Properties Obtained from Optimized Binary Code 181
11.1 Introduction 181
11.2 Timing Analysis of Embedded Systems 183
11.2.1 Simulation 183
11.2.2 Static Analysis 185
11.3 Source-Level Annotation 186
11.4 Reconstruction of Line Information from Binary Code 187
11.5 Implementation and Results 190
11.6 Further Work 194
11.7 Conclusion 194
References 194
Chapter 12 Architecture Specifications in CaSH 197
12.1 Introduction 197
12.2 Preliminary Remarks 199
12.2.1 Hardware Types 199
12.2.2 User Defined Types 200
12.2.3 Operations and Functions 200
12.2.4 Compilation Pipeline 200
12.3 Examples 201
12.3.1 Multiply-Accumulate 201
12.3.2 Remarks 202
12.3.3 Variants of a Fir-filter 202
12.3.4 Variant 1 202
12.3.5 Variant 2 204
12.3.6 Variant 3 204
12.3.7 Remarks 205
12.3.8 Higher Order Cpu 206
12.3.9 Remarks 208
12.3.10 Floating Point Reduction Circuit 208
12.3.11 Remarks 211
12.4 Conclusions and Future Research 211
Reference 211
Chapter 13 SyReC: A Programming Language for Synthesisof Reversible Circuits 213
13.1 Introduction 213
13.2 Reversible Logic 215
13.3 The SyReC Language 217
13.3.1 The Software Language Janus 217
13.3.2 The Hardware Language SyReC 218
13.4 Synthesis of Circuits 219
13.4.1 Reversible Assignment Operations 220
13.4.2 Binary Operations 221
13.4.3 Conditional Statements, Loops, Call/Uncall 222
13.5 Experiments 224
13.6 Conclusions and Future Work 226
References 226
Chapter 14 Logical Time @ Work: Capturing Data Dependencies and Platform Constraints 229
14.1 Introduction 229
14.2 Background 231
14.2.1 ccsl in a Nutshell 231
14.2.2 Process Networks Semantics 233
14.3 Synchronous Data-Flow 234
14.3.1 Semantics Based on Data Dependency 234
14.3.2 Semantics Based on Execution Dependency 235
14.3.2.1 Encoding the Local Scheduling in ccsl 235
14.3.2.2 Local Scheduling Algorithm 237
14.3.3 Semantics Comparison 238
14.4 Extensions to Multidimensional Data-Flow 239
14.4.1 Semantics 239
14.4.2 Encoding MDSDF in ccsl 239
14.5 External Constraints 241
14.6 Discussion and Conclusion 243
References 243
Chapter 15 Formal Support for Untimed MARTE-SystemC Interoperability 245
15.1 Introduction 246
15.2 Related Work 248
15.2.1 ForSyDe 249
15.3 MARTE Specification Methodology 250
15.4 SystemC Model 253
15.5 Formal link Between MARTE and SystemC 255
15.6 Formal Support for Untimed SystemC Models 257
15.7 Conclusions 258
References 258