Handbook of Digital CMOS Technology, Circuits, and Systems (eBook)

Preface 6
There’s Something About Electronics 6
The Signals We Give 7
Analog Circuits 7
Digital Circuits 8
Mixed-Signal Circuits 9
It’s an Abstract Art 10
What is This All About? 12
How to Use This Book 17
Assumptions, Simplifications, Accuracy, and Managing to Do Anything 19
The Formula of the Book 20
The Story as It Is Told 20
Contents 23
1 Devices 27
1.1 The Band Model 27
1.2 Intrinsic Silicon 32
1.3 Band Model with Doping 36
1.4 Extrinsic Silicon 40
1.5 Drift 43
1.6 Diffusion 47
1.7 Forming a Homojunction 49
1.8 PN Junction in Equilibrium 52
1.9 Junction Capacitance 55
1.10 Forward and Reverse Bias 57
1.11 Minority Carrier Injection 59
1.12 Forward-Biased PN Junction Current 61
1.13 Bipolar Junction Transistor 67
1.14 Materials Interfaces 75
1.15 MOS Capacitor Preliminaries 81
1.16 Modes of the MOS Capacitor 84
1.17 MOS Capacitor Characteristics 91
1.18 MOSFET Linear Regime 93
1.19 MOSFET Saturation Regime 94
1.20 Body Effect 100
1.21 Channel Length Modulation 103
2 Ratioed Logic 106
2.1 PMOS 106
2.2 Regions of the MOSFET 107
2.3 BJT Logic 110
2.4 Abandoning BJT 110
2.5 Scaling MOSFET 113
2.6 What is a Logic Family 115
2.7 Resistive Load Inverter 118
2.8 Open-Circuited Transistor 120
2.9 Enhancement Load Inverter 121
2.10 Enhancement Load VTC 122
2.11 Static Power 123
2.12 NAND and NOR Enhancement Load 124
2.13 Random Logic in Enhancement Load 128
2.14 Depletion Load Logic 129
2.15 Pseudo-NMOS Logic 131
2.16 Limitations of Ratioed Logic 132
3 CMOS 135
3.1 Basics of the CMOS Inverter 135
3.2 CMOS VTC 136
3.3 Preliminaries of Delay 140
3.4 MOS Capacitance and Resistance 144
3.5 Simplified Delay Model 147
3.6 Non-static Power 149
3.7 CMOS NAND and NOR 152
3.8 CMOS Complex Logic 154
3.9 Sizing, Delay, and Area 159
3.10 Supply and Width Scaling 165
3.11 Limitations of CMOS 166
4 Logical Effort 168
4.1 Sizing in a Chain 168
4.2 Sizing an Inverter Chain 168
4.3 Gates Versus Inverters: Preliminaries 171
4.4 Normalizing Gate Intrinsic Delay 172
4.5 Normalizing Gate External Delay 173
4.6 Architecture, Inputs, and Effort 175
4.7 Optimal Sizing in a Logic Chain 176
4.8 Logical Effort for Multiple Inputs 179
5 Dynamic Logic 180
5.1 High-Impedance Nodes 180
5.2 Dynamic CMOS and Why it is Great 181
5.3 Delay, Period, and Duty Cycle 185
5.4 Leakage in Dynamic Logic 185
5.5 Charge Sharing 190
5.6 Cascading Dynamic Logic 194
5.7 Logical Effort in Dynamic Gates 198
6 Pipelines 200
6.1 Sequential Versus Combinational 200
6.2 Latches, Registers, and Timing 203
6.3 The Static Register 204
6.4 Dynamic Registers 210
6.5 Imperfect Clocks and Hold-Time 211
6.6 Pipelines, Critical Path, and Slack 215
6.7 Managing Power in a Pipeline 222
6.8 Examples on Pipelining 228
6.9 Impact of Variations 236
7 CMOS Process 239
7.1 Setting and Location 239
7.2 Photolithography Iteration 241
7.3 Account of Materials 243
7.4 Wafer Fabrication 245
7.5 Operations and Equipment 248
7.6 Locos 259
7.7 Advanced Issues in CMOS Processing 269
7.8 Account of Layers 293
8 Design Flow 296
8.1 What Is a Layout 296
8.2 Stick Diagrams 297
8.3 Standard Cells 301
8.4 Design Rules: Foundations 309
8.5 Design Rules—Sample 313
8.6 Fixed-Point Simulation 319
8.7 Physical Design 324
8.8 FPGAs 333
9 HDL 338
9.1 Design Philosophy 338
9.2 The Entity 340
9.3 IEEE Library and std_logic 340
9.4 Types, Attributes, and Operators 343
9.5 Architecture 348
9.6 Structural Connections 348
9.7 Generics and Constants 356
9.8 Multiplexing and Choice 363
9.9 The Process Statement 363
9.10 Signals and Variables 366
9.11 Selection in a Process 368
9.12 Latches and Implicit Latches 369
9.13 Registers and Pipelines 378
9.14 Memories 386
9.15 Counters 390
9.16 State Machines 394
9.17 Testbenches—Preliminaries 400
9.18 Functions and Procedures 402
9.19 Wait, Assertions, and Loops 408
9.20 File I/Os 415
9.21 Packages and Configurations 422
9.22 Good Design Practices 426
10 Scaling 431
10.1 Steep Retrograde Body Effect 431
10.2 Velocity Saturation 432
10.3 MOSFET Leakage 436
10.4 DIBL 442
10.5 MOSFET Structures for DIBL 447
10.6 Miscellaneous Scaling Effects 450
10.7 Impacts on CMOS 455
11 Arithmetic 459
11.1 Binary Addition and Full Adders 459
11.2 Ripple Carry Adder 461
11.3 Generate—Propagate Logic 462
11.4 Carry-Save and Bypass Adders 465
11.5 Lookahead Addition 469
11.6 Group Generates and Propagates 471
11.7 Parallel Prefix Adders 473
11.8 Binary Multiplication 476
11.9 Array Multipliers 477
11.10 Wallace and DADDA Multipliers 479
11.11 Booth Multiplication 484
12 Memories 490
12.1 Architectures and Definitions 490
12.2 NOR ROM Arrays 493
12.3 NAND ROM Arrays 498
12.4 NVMs 501
12.5 SRAM Cell 511
12.6 Sense Amplifiers 515
12.7 SRAM Timing 519
12.8 DRAM Cells 523
12.9 Decoders and Buffers 529
13 Wires and Clocks 538
13.1 Basics 538
13.2 Lumped C Wires 541
13.3 Silicon Wires 543
13.4 Scaling Wires 544
13.5 Interchip Communication 546
13.6 Supply and Ground 552
13.7 Clock Networks 555
13.8 Metastability 559
13.9 Synchronization 565
14 Testing 570
14.1 Fundamentals of Testing 570
14.2 Logical Hazards 578
14.3 Stuck-at Fault Model 586
14.4 Scan Paths 590
14.5 Built in Self-test 595
14.6 IC Packaging and Boundary Scan 599
14.7 Testing Memories 605
14.8 Reliability 608
Glossary 611
Index 651