Low Power Design Essentials (eBook)
XI, 288 Seiten
Springer US (Verlag)
978-0-387-71713-5 (ISBN)
This book contains all the topics of importance to the low power designer. It first lays the foundation and then goes on to detail the design process. The book also discusses such special topics as power management and modal design, ultra low power, and low power design methodology and flows. In addition, coverage includes projections of the future and case studies.
Low Power Design Essentials contains all the topics of importance to the low power designer. The book lays the foundation with background chapters entitled "e;Advanced MOS Transistors and Their Models"e; and "e;Power Basics"e;. These chapters are followed by chapters on the design process including: optimization, architecture and algorithm level, memory, run time, standby logic, and standby memory. Chapters on special topics are also included: power management and modal design, ultra low power, and low power design methodology and flows. The book concludes with a chapter on case studies as well as a chapter on "e;Projection into the Future"e;.These chapters are all based on the extensive amount of teaching that the author has carried out both at universities and companies worldwide. All chapters have been drawn up specifically for self-study. They aim, however, at different levels of understanding. All the chapters start with elementary material, but most also contain advanced material.
Low Power Design Essentials 2
Preface 7
Contents 11
Introduction 12
Slide 1.1 12
Slide 1.2 12
Slide 1.3 13
Slide 1.4 14
Slide 1.5 14
Slide 1.6 15
Slide 1.7 16
Slide 1.8 16
Slide 1.9 17
Slide 1.10 18
Slide 1.11 18
Slide 1.12 19
Slide 1.13 19
Slide 1.14 20
Slide 1.15 20
Slide 1.16 21
Slide 1.17 21
Slide 1.18 22
Slide 1.19 23
Slide 1.20 24
Slide 1.21 25
Slide 1.22 25
Slide 1.23 26
Slide 1.24 27
Slide 1.25 28
Slide 1.26 28
Slide 1.27 29
Slide 1.28 29
Slide 1.29 30
Slide 1.30 31
Slide 1.31 31
Slide 1.32 32
Slide 1.33 32
Slide 1.34 33
Slide 1.35–1.36 33
Nanometer Transistors and Their Models 35
Slide 2.1 35
Slide 2.2 35
Slide 2.3 36
Slide 2.4 36
Slide 2.5 37
Slide 2.6 37
Slide 2.7 38
Slide 2.8 38
Slide 2.9 39
Slide 2.10 39
Slide 2.11 40
Slide 2.12 40
Slide 2.13 41
Slide 2.14 41
Slide 2.15 42
Slide 2.16 42
Slide 2.17 43
Slide 2.18 43
Slide 2.19 44
Slide 2.20 45
Slide 2.21 45
Slide 2.22 45
Slide 2.23 46
Slide 2.24 47
Slide 2.25 47
Slide 2.26 48
Slide 2.27 49
Slide 2.28 49
Slide 2.29 50
Slide 2.30 51
Slide 2.31 51
Slide 2.32 52
Slide 2.33 52
Slide 2.34 53
Slide 2.35 53
Slide 2.36 54
Slide 2.37 54
Slide 2.38 55
Slide 2.39 56
Slide 2.40 56
Slide 2.41 57
Slide 2.42 57
Slide 2.43 58
Slide 2.44 59
Slide 2.45 59
Slide 2.46 60
Slide 2.47 60
Slide 2.48 61
Slide 2.49 62
Slide 2.50 62
Power and Energy Basics 63
Slide 3.1 63
Slide 3.2 63
Slide 3.3 64
Slide 3.4 64
Slide 3.5 65
Slide 3.6 65
Slide 3.7 66
Slide 3.8 66
Slide 3.9 67
Slide 3.10 67
Slide 3.11 68
Slide 3.12 68
Slide 3.13 69
Slide 3.14 69
Slide 3.15 70
Slide 3.16 70
Slide 3.17 70
Slide 3.18 71
Slide 3.19 71
Slide 3.20 72
Slide 3.21 73
Slide 3.22 73
Slide 3.23 74
Slide 3.24 74
Slide 3.25 75
Slide 3.26 75
Slide 3.27 76
Slide 3.28 76
Slide 3.29 77
Slide 3.30 77
Slide 3.31 77
Slide 3.32 78
Slide 3.33 79
Slide 3.34 79
Slide 3.35 80
Slide 3.36 80
Slide 3.37 81
Slide 3.38 81
Slide 3.39 82
Slide 3.40 82
Slide 3.41 83
Slide 3.42 83
Slide 3.43 84
Slide 3.44 84
Slide 3.45 85
Slide 3.46 85
Optimizing Power @ Design Time - Circuit-Level Techniques 86
Slide 4.1 86
Slide 4.2 87
Slide 4.3 87
Slide 4.4 88
Slide 4.5 88
Slide 4.6 89
Slide 4.7 89
Slide 4.8 90
Slide 4.9 91
Slide 4.10 91
Slide 4.11 92
Slide 4.12 92
Slide 4.13 93
Slide 4.14 93
Slide 4.15 94
Slide 4.16 94
Slide 4.17 95
Slide 4.18 95
Slide 4.19 96
Slide 4.20 96
Slide 4.21 97
Slide 4.22 97
Slide 4.23 98
Slide 4.24 98
Slide 4.25 99
Slide 4.26 100
Slide 4.27 101
Slide 4.28 101
Slide 4.29 102
Slide 4.30 102
Slide 4.31 103
Slide 4.32 103
Slide 4.33 104
Slide 4.34 104
Slide 4.35 105
Slide 4.36 105
Slide 4.37 106
Slide 4.38 106
Slide 4.39 107
Slide 4.40 108
Slide 4.41 108
Slide 4.42 108
Slide 4.43 109
Slide 4.44 110
Slide 4.45 110
Slide 4.46 111
Slide 4.47 111
Slide 4.48 112
Slide 4.49 112
Slide 4.50 113
Slide 4.51 113
Slide 4.52 114
Slide 4.53 114
Slide 4.54 115
Slide 4.55 115
Slide 4.56 116
Slide 4.57 116
Slide 4.58 117
Slide 4.59 117
Slide 4.60 118
Slide 4.61 118
Slide 4.62 119
Slide 4.63 and 4.64 119
Optimizing Power @ Design Time - Architecture, Algorithms, and Systems 121
Slide 5.1 121
Slide 5.2 121
Slide 5.3 122
Slide 5.4 122
Slide 5.5 123
Slide 5.6 123
Slide 5.7 124
Slide 5.8 124
Slide 5.9 125
Slide 5.10 125
Slide 5.11 126
Slide 5.12 126
Slide 5.13 127
Slide 5.14 128
Slide 5.15 128
Slide 5.16 129
Slide 5.17 129
Slide 5.18 130
Slide 5.19 130
Slide 5.20 131
Slide 5.21 131
Slide 5.22 131
Slide 5.23 132
Slide 5.24 133
Slide 5.25 133
Slide 5.26 134
Slide 5.27 134
Slide 5.28 135
Slide 5.29 136
Slide 5.30 136
Slide 5.31 136
Slide 5.32 137
Slide 5.33 137
Slide 5.34 138
Slide 5.35 139
Slide 5.36 139
Slide 5.37 140
Slide 5.38 140
Slide 5.39 140
Slide 5.40 141
Slide 5.41 141
Slide 5.42 142
Slide 5.43 143
Slide 5.44 143
Slide 5.45 143
Slide 5.46 144
Slide 5.47 144
Slide 5.48 145
Slide 5.49 146
Slide 5.50 146
Slide 5.51 147
Slide 5.52 147
Slide 5.53 148
Slide 5.54 148
Slide 5.55 149
Slide 5.56 149
Slide 5.57 149
Slide 5.58 150
Slide 5.59 151
Slide 5.60 151
Slide 5.61 152
Slide 5.62 152
Slide 5.63 153
Slide 5.64 153
Slide 5.65 153
Slide 5.66 154
Slide 5.67 155
Slide 5.68 155
Slide 5.69 156
Slides 5.70 and 5.71 156
Optimizing Power @ Design Time - Interconnect and Clocks 158
Slide 6.1 158
Slide 6.2 158
Slide 6.3 159
Slide 6.4 159
Slide 6.5 159
Slide 6.6 160
Slide 6.7 161
Slide 6.8 161
Slide 6.9 162
Slide 6.10 163
Slide 6.11 163
Slide 6.12 164
Slide 6.13 164
Slide 6.14 165
Slide 6.15 165
Slide 6.16 166
Slide 6.17 166
Slide 6.18 167
Slide 6.19 167
Slide 6.20 168
Slide 6.21 168
Slide 6.22 169
Slide 6.23 170
Slide 6.24 170
Slide 6.25 171
Slide 6.26 172
Slide 6.27 172
Slide 6.28 173
Slide 6.29 174
Slide 6.30 174
Slide 6.31 175
Slide 6.32 176
Slide 6.33 176
Slide 6.34 177
Slide 6.35 177
Slide 6.36 179
Slide 6.37 179
Slide 6.38 180
Slide 6.39 180
Slide 6.40 181
Slide 6.41 181
Slide 6.42 182
Slide 6.43 183
Slide 6.44 184
Slide 6.45 184
Slide 6.46 185
Slide 6.47 185
Slide 6.48 186
Slide 6.49 187
Slides 6.50–6.52 187
Optimizing Power @ Design Time - Memory 189
Slide 7.1 189
Slide 7.2 190
Slide 7.3 190
Slide 7.4 191
Slide 7.5 191
Slide 7.6 191
Slide 7.7 192
Slide 7.8 193
Slide 7.9 194
Slide 7.10 195
Slide 7.11 195
Slide 7.12 196
Slide 7.13 197
Slide 7.14 197
Slide 7.15 198
Slide 7.16 199
Slide 7.17 199
Slide 7.18 200
Slide 7.19 201
Slide 7.20 201
Slide 7.21 202
Slide 7.22 203
Slide 7.23 204
Slide 7.24 204
Slide 7.25 205
Slide 7.26 205
Slide 7.27 206
Slide 7.28 207
Slide 7.29 207
Slide 7.30 208
Slide 7.31 209
Slide 7.32 209
Slide 7.33 210
Slide 7.34 211
Slides 7.35–7.37 212
Optimizing Power @ Standby - Circuits and Systems 213
Slide 8.1 213
Slide 8.2 214
Slide 8.3 214
Slide 8.4 215
Slide 8.5 215
Slide 8.6 216
Slide 8.7 216
Slide 8.8 217
Slide 8.9 217
Slide 8.10 218
Slide 8.11 218
Slide 8.12 219
Slide 8.13 220
Slide 8.14 220
Slide 8.15 221
Slide 8.16 221
Slide 8.17 222
Slide 8.18 222
Slide 8.19 223
Slide 8.20 223
Slide 8.21 224
Slide 8.22 224
Slide 8.23 225
Slide 8.24 225
Slide 8.25 225
Slide 8.26 226
Slide 8.27 226
Slide 8.28 227
Slide 8.29 227
Slide 8.30 228
Slide 8.31 228
Slide 8.32 229
Slide 8.33 230
Slide 8.34 230
Slide 8.35 231
Slide 8.36 231
Slide 8.37 232
Slide 8.38 232
Slide 8.39 233
Slide 8.40 233
Slide 8.41 234
Slide 8.42 234
Slide 8.43 235
Slide 8.44 235
Slide 8.45 235
Slide 8.46 236
Slides 8.47 and 8.48 237
Optimizing Power @ Standby - Memory 238
Slide 9.1 238
Slide 9.2 238
Slide 9.3 239
Slide 9.4 240
Slide 9.5 240
Slide 9.6 240
Slide 9.7 241
Slide 9.8 242
Slide 9.9 242
Slide 9.10 243
Slide 9.11 243
Slide 9.12 244
Slide 9.13 244
Slide 9.14 245
Slide 9.15 246
Slide 9.16 246
Slide 9.17 247
Slide 9.18 248
Slide 9.19 248
Slide 9.20 249
Slide 9.21 250
Slide 9.22 250
Slide 9.23 250
Slide 9.24 251
Slide 9.25 252
Slides 9.26–9.28 253
Optimizing Power @ Runtime - Circuits and Systems 254
Slide 10.1 254
Slide 10.2 255
Slide 10.3 255
Slide 10.4 255
Slide 10.5 256
Slide 10.6 256
Slide 10.7 257
Slide 10.8 258
Slide 10.9 258
Slide 10.10 259
Slide 10.11 259
Slide 10.12 259
Slide 10.13 260
Slide 10.14 261
Slide 10.15 261
Slide 10.16 262
Slide 10.17 262
Slide 10.18 263
Slide 10.19 263
Slide 10.20 264
Slide 10.21 265
Slide 10.22 265
Slide 10.23 266
Slide 10.24 266
Slide 10.25 266
Slide 10.26 267
Slide 10.27 268
Slide 10.28 268
Slide 10.29 269
Slide 10.30 269
Slide 10.31 270
Slide 10.32 270
Slide 10.33 271
Slide 10.34 271
Slide 10.35 272
Slide 10.36 272
Slide 10.37 273
Slide 10.38 274
Slide 10.39 274
Slide 10.40 275
Slide 10.41 275
Slide 10.42 276
Slide 10.43 276
Slide 10.44 277
Slide 10.45 278
Slide 10.46 279
Slide 10.47 279
Slide 10.48 280
Slide 10.49 281
Slide 10.50 281
Slide 10.51 281
Slide 10.52 282
Slide 10.53 283
Slide 10.54 284
Slide 10.55 284
Slide 10.56 285
Slide 10.57 285
Slide 10.58 286
Slide 10.59 287
Slide 10.60 287
Slide 10.61 288
Slide 10.62 288
Slide 10.63 289
Slide 10.64 290
Slide 10.65 291
Slide 10.66 291
Slide 10.67–10.69 292
Ultra Low Power/Voltage Design 294
Slide 11.1 294
Slide 11.2 294
Slide 11.3 295
Slide 11.4 295
Slide 11.5 296
Slide 11.6 297
Slide 11.7 297
Slide 11.8 297
Slide 11.9 298
Slide 11.10 298
Slide 11.11 299
Slide 11.12 300
Slide 11.13 301
Slide 11.14 301
Slide 11.15 302
Slide 11.16 302
Slide 11.17 302
Slide 11.18 303
Slide 11.19 304
Slide 11.20 304
Slide 11.21 304
Slide 11.22 305
Slide 11.23 306
Slide 11.24 306
Slide 11.25 306
Slide 11.26 307
Slide 11.27 308
Slide 11.28 308
Slide 11.29 308
Slide 11.30 309
Slide 11.31 310
Slide 11.32 310
Slide 11.33 311
Slide 11.34 311
Slide 11.35 312
Slide 11.36 312
Slide 11.37 312
Slide 11.38 313
Slide 11.39 313
Slide 11.40 314
Slide 11.41 315
Slide 11.42 315
Slide 11.43 316
Slide 11.44 316
Slide 11.45 317
Slide 11.46 318
Slide 11.47 318
Slide 11.48 318
Slide 11.49 319
Slide 11.50 320
Slide 11.51 320
Slide 11.52 320
Slides 11.53–11.54 321
Low Power Design Methodologies and Flows 322
Slide 12.1 322
Slide 12.2 322
Slide 12.3 323
Slide 12.4 324
Slide 12.5 324
Slide 12.6 325
Slide 12.7 326
Slide 12.8 326
Slide 12.9 327
Slide 12.10 327
Slide 12.11 328
Slide 12.12 328
Slide 12.13 329
Slide 12.14 329
Slide 12.15 330
Slide 12.16 331
Slide 12.17 331
Slide 12.18 332
Slide 12.19 332
Slide 12.20 332
Slide 12.21 333
Slide 12.22 334
Slide 12.23 334
Slide 12.24 335
Slide 12.25 335
Slide 12.26 335
Slide 12.27 336
Slide 12.28 336
Slide 12.29 337
Slide 12.30 337
Slide 12.31 338
Slide 12.32 338
Slide 12.33 339
Slide 12.34 340
Slide 12.35 340
Slide 12.36 341
Slide 12.37 341
Slide 12.38 342
Slide 12.39 342
Slide 12.40 343
Slide 12.41 343
Slide 12.42 344
Slide 12.43 344
Slide 12.44 345
Slide 12.45 345
Slide 12.46 346
Slide 12.47 346
Slide 12.48 347
Slide 12.49 347
Slide 12.50 348
Slide 12.51 348
Slide 12.52 349
Summary and Perspectives 350
Slide 13.1 350
Slide 13.2 350
Slide 13.3 351
Slide 13.4 351
Slide 13.5 352
Slide 13.6 352
Slide 13.7 353
Slide 13.8 354
Slide 13.9 354
Slide 13.10 355
Slide 13.11 356
Slide 13.12 357
Slide 13.13 357
Slide 13.14 358
Slide 13.15 359
Slide 13.16 359
Slide 13.17 360
Index 361
Nanometer Transistors and Their Models 35
2.1 Slide 2.1 35
2.2 Slide 2.2 35
2.3 Slide 2.3 36
2.4 Slide 2.4 36
2.5 Slide 2.5 37
2.6 Slide 2.6 37
2.7 Slide 2.7 38
2.8 Slide 2.8 38
2.9 Slide 2.9 39
2.10 Slide 2.10 39
2.11 Slide 2.11 40
2.12 Slide 2.12 40
2.13 Slide 2.13 41
2.14 Slide 2.14 41
2.15 Slide 2.15 42
2.16 Slide 2.16 42
2.17 Slide 2.17 43
2.18 Slide 2.18 43
2.19 Slide 2.19 44
2.20 Slide 2.20 45
2.21 Slide 2.21 45
2.22 Slide 2.22 45
2.23 Slide 2.23 46
2.24 Slide 2.24 47
2.25 Slide 2.25 47
2.26 Slide 2.26 48
2.27 Slide 2.27 49
2.28 Slide 2.28 49
2.29 Slide 2.29 50
2.30 Slide 2.30 51
2.31 Slide 2.31 51
2.32 Slide 2.32 52
2.33 Slide 2.33 52
2.34 Slide 2.34 53
2.35 Slide 2.35 53
2.36 Slide 2.36 54
2.37 Slide 2.37 54
2.38 Slide 2.38 55
2.39 Slide 2.39 56
2.40 Slide 2.40 56
2.41 Slide 2.41 57
2.42 Slide 2.42 57
2.43 Slide 2.43 58
2.44 Slide 2.44 59
2.45 Slide 2.45 59
2.46 Slide 2.46 60
2.47 Slide 2.47 60
2.48 Slide 2.48 61
2.49 Slide 2.49 62
2.50 Slide 2.50 62
| Erscheint lt. Verlag | 21.4.2009 |
|---|---|
| Reihe/Serie | Integrated Circuits and Systems |
| Zusatzinfo | XII, 288 p. 222 illus. in color. |
| Verlagsort | New York |
| Sprache | englisch |
| Themenwelt | Naturwissenschaften ► Physik / Astronomie |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | advanced MOS transistors • Digital Design • Interconnect • Logic • low power design methodologies and flows • Material • optimizing power at design time • optimizing power at runtime • optimizing power at standby • power management • Transistor • Ultra-low power and • Ultra-low power and voltage design |
| ISBN-10 | 0-387-71713-7 / 0387717137 |
| ISBN-13 | 978-0-387-71713-5 / 9780387717135 |
| Haben Sie eine Frage zum Produkt? |
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