High Dielectric Constant Materials (eBook)

Preface 6
Contents 9
List of Contributors 20
1 The Economic Implications of Moore’s Law 24
1.1 Introduction 24
1.2 Moore’s Law: A Description 24
1.3 The History of Moore’s Law 25
1.4 The Microeconomics of Moore’s Law 36
1.5 The Macroeconomics of Moore’s Law 44
1.6 Moore’s Law Meets Moore’s Wall: What is Likely to Happen 46
1.7 Conclusion 50
1.8 Appendix A 51
References 53
Classical Regime for SiO2 54
2 Brief Notes on the History of Gate Dielectrics in MOS Devices 55
2.1 Early Attempts to Make Insulating- Gate Field- Effect Transistors Surface States
2.2 Passivation of Silicon Surfaces by Thermal Oxidation Planar Transistor Technology
2.3 Positive Oxide Charge and Surface States at the Si– SiO2 Interface 57
2.4 Instabilities Due to Ion Drift Effects 58
2.5 Phosphate-silicate Glass Helped 59
2.6 Other Materials Tried as Gate-Dielectric Layers 59
2.7 Thermal Oxidation of Silicon 60
2.8 Segregation of Dopants at the Si– SiO2 Interface 61
2.9 Other Silicon Oxide Preparation Techniques 62
2.10 Thick Field Oxides 63
2.11 Breakdown Strength of SiO2, Defect Density, Moore’s Law 63
2.12 Weak Oxide Regions in MOS Structures, Kooi Effect 63
2.13 Al Gate MOS Devices PMOS IC’s
2.14 Silicon Gate MOS Devices, NMOS and CMOS IC’s 64
2.15 Decrease of Oxide Thickness Connected with Downscaling of MOS Structure 65
References 65
3 SiO2 Based MOSFETS: Film Growth and Si– SiO2 Interface Properties 67
3.1 SiO2 Prior to 1970 67
3.2 After 1970: Progress in Understanding 77
3.3 Modern Era: The Quest for Thinner SiO2 and Alternatives 98
References 108
4 Oxide Reliability Issues 113
4.1 Thin Oxide Layer Degradation Under Electrical Stress 113
4.2 Oxide Breakdown 124
4.3 Breakdown Acceleration Models 129
4.4 Conclusion 133
References 133
Transition to Silicon Oxynitrides 143
5 Gate Dielectric Scaling to 2.0–1.0 nm: SiO2 and Silicon Oxynitride 144
5.1 Device Requirements on Gate Dielectric Scaling 144
5.2 Definition of Gate Dielectric Thickness 148
5.3 Tunneling Current of SiO2 153
5.4 Tunneling Currents of Silicon Oxynitride 156
5.5 Application Dependence of Gate Dielectric Limit 158
References 161
6 Optimal Scaling Methodologies and Transistor Performance 164
6.1 Introduction 164
6.2 Scaling and Device Physics 166
6.3 Limitations of Conventional Scaling 175
6.4 Extending Validity of Moore’s Law 186
6.5 Conclusions 211
References 213
7 Silicon Oxynitride Gate Dielectric for Reducing Gate Leakage and Boron Penetration Prior to High- k Gate Dielectric Implementation 216
7.1 Introduction 216
7.2 Integrated RTCVD Oxynitride (ION) Process 218
7.3 JVD Nitride 228
7.4 DPN Oxynitride 232
7.5 Conclusion 239
References 240
Transition to High-k Gate Dielectrics 242
8 Alternative Dielectrics for Silicon- Based Transistors: Selection Via Multiple Criteria 243
8.1 Introduction 243
8.2 Discussion 246
8.3 Conclusions 267
References 268
9 Materials Issues for High- k Gate Dielectric Selection and Integration 272
9.1 Introduction 272
9.2 MIS (Metal-Insulator-Semiconductor) Structures 276
9.3 Materials Properties and Integration Considerations 280
9.4 Conclusions 296
References 296
10 Designing Interface Composition and Structure in High Dielectric Constant Gate Stacks 306
10.1 Introduction 306
10.2 Thermodynamic Stability of Dielectrics on Silicon 309
10.3 Kinetic Rate Processes During Metal Oxide Deposition 316
10.4 Gate Electrode/Dielectric Interfaces 323
10.5 Conclusion 324
References 325
11 Electronic Structure of Alternative High- k Dielectrics 330
11.1 Introduction 330
11.2 SiO2 and the Si–SiO2 Interface 332
11.3 Alternative Dielectrics 341
11.4 Electronic Structure of Transition Metal Dielectrics 346
11.5 Experimental Studies of Electronic Structure 352
11.6 Interface Electronic Structure Applied to Direct Tunneling in Silicate Alloys 367
11.7 Conclusion 372
References 374
12 Physicochemical Properties of Selected 4d, 5d, and Rare Earth Metals in Silicon 377
12.1 Introduction 377
12.2 Crystal Lattice Site of 4d, 5d, and Rare Earth Metals in Silicon 378
12.3 Solubility of 4d, 5d, and Rare Earth Metals in Silicon 379
12.4 Diffusivity of 4d, 5d, and Rare Earth Elements in Silicon 380
12.5 Energy Levels in the Band Gap 386
12.6 Effect of 4d, 5d, and Rare Earth Metals on Minority Carrier Recombination Lifetime and Device Performance 390
12.7 Summarizing Discussion 392
References 393
13 High-k Gate Dielectric Deposition Technologies 397
13.1 Atomic Layer Deposition 398
13.2 Chemical Vapor Deposition 409
13.3 Plasma-Enhanced Atomic Layer Deposition 411
13.4 Plasma Enhanced Chemical Vapor Deposition 414
13.5 Physical Vapor Deposition 417
13.6 Molecular Beam Epitaxy 421
13.7 Ion Beam Assisted Deposition 422
13.8 Sol-gel Deposition 423
13.9 Summary 424
References 425
14 Issues in Metal Gate Electrode Selection for Bulk CMOS Devices 432
14.1 Background 432
14.2 Metal Gate Selection Criteria 433
14.3 Other Challenges with Metal Gates 435
14.4 Metal Gate Candidates for NMOS Devices 436
14.5 Metal Candidates for PMOS Devices 447
14.6 Metals on High-k Dielectrics 447
14.7 Conclusion 448
References 449
15 CMOS IC Fabrication Issues for High- k Gate Dielectric and Alternate Electrode Materials 452
15.1 Introduction 452
15.2 The "Standard” CMOS Flow 453
15.3 Insertion of High-k Gate Dielectric into the CMOS Flow 459
15.4 Alternative Electrode Materials 466
15.5 Integration of High-k Gate Dielectrics and Metal Gates into Advanced Devices 478
15.6 Conclusions 487
References 488
16 Characterization and Metrology of Medium Dielectric Constant Gate Dielectric Films 499
16.1 Introduction 499
16.2 Structural and Chemical Characterization of Medium e Film Stacks 502
16.3 Optical Models for Medium k Films 519
References 533
17 Electrical Measurement Issues for Alternative Gate Stack Systems 537
17.1 Introduction 537
17.2 Capacitance–Voltage Measurement 538
17.3 Analysis of Device/Material Parameters from Established C– V Data 564
17.4 Current-Voltage Measurement 567
17.5 Determination of DC Conduction Mechanisms 572
17.6 Sample Design and Preparation Issues 576
17.7 Conclusion 578
References 578
18 High-k Gate Dielectric Materials Integrated Circuit Device Design Issues 583
18.1 Introduction 583
18.2 Fundamental Issues on Gate Capacitance and Current Modeling 584
18.3 Wave Function Penetration Effect Issues 595
18.4 Maxwell–Wagner Effects and Power Law Dispersion 607
18.5 Conclusions 618
References 619
Future Directions for Ultimate Scaling Technology Generations 621
19 High-k Crystalline Gate Dielectrics: A Research Perspective 622
19.1 Introduction 622
19.2 The Path to the Perovskites and COS 625
19.3 The Material System of COS 629
19.4 The Implementation of COS 634
19.5 Electrical Properties 644
19.6 Conclusion 649
References 650
20 High-k Crystalline Gate Dielectrics: An IC Manufacturer’s Perspective 653
20.1 Introduction 653
20.2 Theoretical Overview 658
20.3 Perovskite Surface 658
20.4 Oxide Deposition 661
20.5 Growth Template 662
20.6 Substrate Preparation 663
20.7 Initial Nucleation 664
20.8 Stability of the Interface 667
20.9 Structural Properties 668
20.10 Band Discontinuity 672
20.11 Device Results 675
20.12 Conclusion 677
References 678
21 Advanced MOS-Devices 681
21.1 Introduction 681
21.2 The Ballistic Nanotransistor 688
21.3 Vertical Replacement Gate MOSFET 695
21.4 The Double-Gate FinFET 702
21.5 Silicon-On-Nothing MOSFETs 706
21.6 Conclusion 715
References 716
Index 720