VLSI-Design of Non-Volatile Memories (eBook)

Preface 5
Acknowledgements 7
Contents 8
Foreword: Non- Volatile Memory Technology Evolution 15
Systems Needs for Non-Volatile Storage 16
NOR Flash Memory 19
NAND Flash Memory 21
New Memory Concepts 23
Conclusions 26
1 Non-Volatile Memory Design 27
1.1 Introduction 27
1.2 Main Features of Non-Volatile Memories 28
1.3 Program 29
1.4 Erase 30
1.5 Distributions and Cycles 30
1.6 Read Mode Architecture 33
1.7 Write Mode Architecture 34
1.8 Erase Mode Architecture 35
1.9 Elements of Reliability 36
1.10 Influence of Temperature and Supply Voltage 36
1.11 Lab Activities 37
1.12 Working Tools 38
1.13 Shmoo Plots 40
1.14 Testing 42
1.15 Memory Pins Description 42
Bibliography 45
2 Process Aspects 47
2.1 Introduction 47
2.2 Main Steps of Fabrication for a CMOS Process 47
Bibliography 59
3 The MOSFET Transistor and the Memory Cell 61
3.1 The MOSFET Transistor 61
3.2 Transistors Available 65
3.3 The Memory Cell 70
3.4. Reading Characteristics 74
3.5 Programming 76
3.6 Program Algorithm 83
3.7 Erase Operation 85
3.8 Erase Algorithm 94
Bibliography 95
4 Passive Components 97
4.1 MOS Capacitors 97
4.2 CMOS Technology Capacitors 99
4.3 Integrated Resistors 102
Bibliography 105
5 Fundamental Circuit Blocks 106
5.1 Introduction 106
5.2 NMOS and CMOS Inverters 106
5.3 The Cascode 112
5.4 Differential Stage 115
5.5 The Source Follower 119
5.6 Voltage References 121
5.7 Current Mirrors 131
5.8 NMOS and CMOS Schmitt Trigger 134
5.9 Voltage Level Shifter Latch 139
5.10 Power On Reset Circuits 140
5.11 Analog Switch 144
5.12 Bootstrap 148
5.13 Oscillators 156
5.14 Circuits to Detect Third Level Signals 160
5.15 VDD Low Detector 162
Bibliography 163
6 Layout 165
6.1 Custom Layout 165
6.2 A Three-Inputs NAND 165
6.3 A Three-Inputs NOR 168
6.4 An Interdigitized Inverter and a Capacitor 168
6.5 Area and Perimeter Parasitic Capacitances 170
6.6 Automatic Layout 171
Bibliography 173
7 The Organization of the Memory Array 175
7.1 Introduction: EPROM Memories 175
7.2 Flash Memory Organization: The Sectors 175
7.3 An Array of Sectors 182
7.4 Other Types of Array 183
Bibliography 189
8 The Input Buffer 190
8.1 A Discussion on Input and Output Levels 190
8.2 Input Buffers 191
8.3 Examples of Input Buffers 193
8.4 Automatic Stand-By Mode 195
Bibliography 197
9 Decoders 198
9.1 Introduction 198
9.2 Word Line Capacitance and Resistance 202
9.3 Row Decoders 207
9.4 NMOS Row Decoder 213
9.5 CMOS Row Decoders 216
9.6 A Dynamic CMOS Row Decoding 218
9.7 A Semistatic CMOS Row Decoder 220
9.8 Row Decoders for Low Supply Voltage 222
9.9 Row Pre-Decoder at High Voltage 225
9.10 Sector Decoding 226
9.11 Memory Space for Test: The OTP Rows 228
9.12 Hierarchical Row Decoding 229
9.13 Low Switching Consumption Row Decoder 234
9.14 Column Decoders 236
Bibliography 238
10 Boost 240
10.1 Introduction 240
10.2 Boost Techniques 240
10.3 One-Shot Local Boost 243
10.4 Double-Boost Row Decoder 247
10.5 The Issue of the Recharge of CBOOST 250
10.6 Double-Path Boost Circuitry 253
10.7 Boosted Voltages Switch 256
10.8 Leakage Recovery Circuits 259
Bibliography 261
11 Synchronization Circuits 262
11.1 ATD 262
11.2 Multiple ATD Management 264
11.3 Let’s Connect the ATD to the Boost Circuitry 266
11.4 Equalization of the Sense Amplifier: SAEQ 268
11.5 The ENDREAD Signal 273
11.6 The Cells Used by the Dummy Sense Amplifiers 275
11.7 ATD – ENDREAD Overlap 275
11.8 Sequential Reads 276
Bibliography 290
12 Reading Circuits 291
12.1 The Inverter Approach 291
12.2 Differential Read with Unbalanced Load 295
12.3 Differential Reading with Current Offset 299
12.4 Semi-Parallel Reference Current 301
12.5 Techniques to Speed Up Read 305
12.6 Differential Read with Current Mirror 309
12.7 The Flash Cell 311
12.8 Reading at Low VDD 312
12.9 Amplified I/V Converter 315
12.10 Amplified Semi-Parallel Reference 316
12.11 Sizing of the Main Mirror 318
12.12 Dynamic Analysis of the Sense Amplifier 320
12.13 Precharge of the Output Stage of the Comparator 323
12.4 Issues of the Reference 324
12.15 Mirrored Reference Current 326
12.16 The Verify Operation 328
Bibliography 331
13 Multilevel Read 334
13.1 Multilevel Storage 334
13.2 Current Sensing Method 336
13.3 Multilevel Programming 339
13.4 Current/Voltage Reference Network 340
13.5 Voltage Sensing Method 343
13.6 Sample & Hold Sense Amplifier
13.7 Closed-Loop Voltage Sensing 350
13.8 Hierarchical Row Decoding for Multiple Sensing Loops 353
13.9 A/D Conversion 356
13.10 Low Power Comparator 359
Bibliography 361
14 Program and Erase Algorithms 363
14.1 Memory Architecture from the Program-Erase Functionality Point of View 363
14.2 User Command to Program and Erase 366
14.3 Program Algorithm for Bi-Level Memories 367
14.4 Program Algorithm for Multilevel Memories 371
14.5 Erase Algorithm 376
14.6 Test Algorithms 379
Bibliography 380
15 Circuits Used in Program and Erase Operations 381
15.1 Introduction 381
15.2 Dual Voltage Devices 382
15.3 Charge Pumps 384
15.4 Different Types of Charge Pumps 390
15.5 High Voltage Limiter 401
15.6 Charge Pumps for Negative Voltages 403
15.7 Voltage Regulation Principles 404
15.8 Gate Voltage Regulation 404
15.9 Drain Voltage Regulation and Temperature Dependence 421
Bibliography 426
16 High-Voltage Management System 428
16.1 Introduction 428
16.2 Sectors Biasing 428
16.3 Local Sector Switch 433
16.4 Stand-By Management 436
16.5 High-Voltage Management 442
16.6 Modulation Effects 448
Bibliography 459
17 Program and Erase Controller 461
17.1 FSM Controller 461
17.2 STD Cell Implementation of the FSM 462
17.3 PLA Implementation of the FSM 463
17.4 Microcontroller 465
Bibliography 472
18 Redundancy and Error Correction Codes 473
18.1 Redundancy 473
18.2 Redundancy & Read Path
18.3 Yield 477
18.4 UPROM Cells 482
18.5 The First Read After Power On Reset 488
18.6 Error Correction Codes 491
Bibliography 496
19 The Output Buffer 499
19.1 Introduction 499
19.2 NMOS Output Buffer 502
19.3 A CMOS Super Output Buffer 503
19.4 The “High Voltage Tolerance” Issue 506
19.5 Noise Induced on the Signal Circuitry by Commutation of the Output Buffers 511
Bibliography 519
20 Test Modes 520
20.1 Introduction 520
20.2 An Overview on Test Modes 520
20.3 DMA Test 522
20.4 Fast DMA 524
20.5 Oxide Integrity Test 524
Bibliography 526
21 ESD & Latch-Up
21.1 Notes on Bipolar Transistors 527
21.2 Latch-Up 532
21.3 Bipolar Transistors Used in Flash Memories 534
21.4 Distribution of Power Supplies and ESD Protection Network 536
Bibliography 539
22 From Specification Analysis to Floorplan Definition 540
22.1 Introduction 540
22.2 Matrix Organization 540
22.3 Matrix Row Dimensioning 545
22.4 Dimensioning the Sectors 548
22.5 Memory Configurations 550
22.6 Organization of Column Decoding 551
22.7 Redundancy 553
22.8 First Considerations on Read Mode 555
22.9 Architecture of the Reference 557
22.10 Read Problems for a Non-Static Memory 558
22.11 Erase and Program Circuits 559
22.12 Pad Placement 562
22.13 Control Logic and Related Circuitry 564
Bibliography 565
23 Photo Album 566
23.1 Introduction 566
23.2 Figures Index 566
23.3 The Photos 567
Subject Index 590