3-Dimensional VLSI (eBook)
200 Seiten
Springer Berlin (Verlag)
978-3-642-04157-0 (ISBN)
'3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme'elaborates the concept and importance of 3-Dimensional (3-D) VLSI. The authors have developed a new 3-D IC integration paradigm, so-called 2.5-D integration, to address many problems that are hard to resolve using traditional non-monolithic integration schemes. The book also introduces major 3-D VLSI design issues that need to be solved by IC designers and Electronic Design Automation (EDA) developers. By treating 3-D integration in an integrated framework, the book provides important insights for semiconductor process engineers, IC designers, and those working in EDA R&D.
Dr. Yangdong Deng is an associate professor at the Institute of Microelectronics, Tsinghua University, China. Dr. Wojciech P. Maly is the U. A. and Helen Whitaker Professor at the Department of Electrical and Computer Engineering, Carnegie Mellon University, USA.
Title page 2
Copyright Page 3
Preface 6
Acknowledgements 8
Table of Contents 9
List of Figures and Tables 13
1 Introduction 17
1.1 2.5-D Integration 21
1.2 Enabling Technologies 24
1.2.1 Fabrication Technology 24
1.2.2 Testing Methodology and Fault Tolerance Technique 25
1.2.3 Design Technology 26
1.3 Objectives and Book Organization 29
References 32
2 A Cost Comparison of VLSI Integration Schemes 37
2.1 Non-Monolithic Integration Schemes 38
2.1.1 Multiple-Reticle Wafer 39
2.1.2 Multiple Chip Module (MCM) 39
2.1.3 Three-Dimensional (3-D) integration 40
2.2 Yield Analysis of Different VLSI Integration Approaches 42
2.2.1 Monolithic Soc 44
2.2.2 Multiple-Reticle Wafer (MRW) 44
2.2.3 Three-Dimensional (3-D) Integration 46
2.2.4 2.5-D System Integration 47
2.2.5 Multi-Chip Module 50
2.2.6 Summing Up 51
2.3 Observations 53
References 54
3 Design Case Studies 58
3.1 Crossbar 59
3.2 A 2.5-D Rambus DRAM Architecture 62
3.2.1 Tackle the Long Bus Wire 62
3.2.2 Serialized Channel in the 3rd Dimension 64
3.3 A 2.5-D Redesign of PipeRench 66
3.3.1 The 2.5-D Implementation 68
3.3.2 Simulation Results 70
3.4 A 2.5-D Integrated Microprocessor System 72
3.4.1 A 2.5-D Integrated Microprocessor System 73
3.4.2 An Analytical Performance Model 78
3.4.3 Detailed Performance Simulation for Reduced Memory Latency 82
3.5 Observations 85
References 87
4 An Automatic 2.5-D Layout Design Flow 90
4.1 A 2.5-D Layout Design Framework 91
4.1.1 2.5-D Floorplanning 93
4.1.2 2.5-D Placement 94
4.1.3 2.5-D Global Routing 94
4.2 Observations 97
References 97
5 Floorplanning for 2.5-D Integration 99
5.1 Floorplan Level Evaluation—Category 2 Circuits 103
5.1.1 Technique 103
5.1.2 Results 105
5.2 Floorplan Level Evaluation—Category 3 Circuits 107
5.2.1 Technique 107
5.2.2 Results 108
5.3 Thermal driven floorplanning 109
5.3.1 Chip Level Thermal Modeling and Analysis for 2.5-D Floorplanning 111
5.3.2 Coupled Temperature and Leakage Estimation 115
5.3.3 2.5-D Thermal Driven Floorplanning Techniques 121
5.3.4 Experimental results 123
5.4 Observations 127
References 129
6 Placement for 2.5-D Integration 133
6.1 Pure Standard Cell Designs 135
6.1.1 Placement Techniques 136
6.1.2 Benchmarks and Layout Model 139
6.1.3 Evaluation of Vertical Partitioning Strategies 141
6.1.4 Wire length scaling 142
6.1.5 Wire length reduction 145
6.1.6 Wire Length vs. Inter-Chip Contact Pitch 149
6.2 Mixed Macro and Standard Cell Designs 150
6.2.1 Placement Techniques 152
6.2.2 Results and Analysis 154
6.3 Observations 156
References 158
7 A Road map of 2.5-D Integration 160
7.1 Stacked Memory 161
7.2 DRAM Integration for Bandwidth-Demanding Applications 163
7.3 Hybrid System Integration 167
7.4 Extremely High Performance Systems 171
7.4.1 Highly Integrated Image Sensor System 171
7.4.2 Radar-in-Cube 174
References 176
8 Conclusion and Future Work 180
8.1 Main Contributions and Conclusions 181
8.2 Future Work 184
8.2.1 Fabrication Technology for 2.5-D Systems 185
8.2.2 Testing Techniques for 2.5-D Integration 187
8.2.3 Design Technology for 2.5-D Integration 189
8.2.3.1 2.5-D Architecture Exploration tools 190
8.2.3.2 System Level Design Tools 194
8.2.3.3 Physical Design Tool Suite for 2.5-D ASICs 195
8.2.3.4 2.5-D VLSI Design Flow 199
References 202
Index 204
| Erscheint lt. Verlag | 8.9.2010 |
|---|---|
| Zusatzinfo | 200 p. 50 illus. |
| Verlagsort | Berlin |
| Sprache | englisch |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| Schlagworte | 2.5-D integration • 3-D integration • design automation • Electronic Design Automation • Integrated circuit • Integrated Circuits • semiconductor • TUP • Very-large-scale integration • VLSI • VLSI Design • VLSI IC |
| ISBN-10 | 3-642-04157-4 / 3642041574 |
| ISBN-13 | 978-3-642-04157-0 / 9783642041570 |
| Haben Sie eine Frage zum Produkt? |
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