Extreme Statistics in Nanoscale Memory Design (eBook)

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2010 | 2010
X, 246 Seiten
Springer US (Verlag)
978-1-4419-6606-3 (ISBN)

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Knowledge exists: you only have to ?nd it VLSI design has come to an important in?ection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacri?ce too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can ?nd the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5-6s (0.
Knowledge exists: you only have to ?nd it VLSI design has come to an important in?ection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacri?ce too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can ?nd the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5-6s (0.

Extreme Statistics in Nanoscale Memory Design 3
Preface 5
Contents 7
Contributors 9
Chapter 1: Introduction 11
1.1 Yield-Driven Design: Need for Accurate Yield Estimation 11
1.2 The Case of High-Replication Circuits 12
1.3 Why Does Standard Monte Carlo Not Work? 13
1.3.1 Process Variation Statistics: Prerequisites for Statistical Analysis 14
1.3.2 Monte Carlo Simulation 14
1.3.3 The Problem with Memories 15
1.4 An Overview of This Book 15
References 18
Chapter 2: Extreme Statistics in Memories 19
2.1 Cell Failure Probability: An Extreme Statistic 19
2.1.1 Units of Failure Probability 21
2.1.2 An Example of Extreme Statistics in Memories 21
2.2 Incorporating Redundancy 22
2.2.1 The Poisson Yield Model 23
2.2.1.1 An Example: Quantifying Fault Tolerance with Statistical Analysis 24
Reference 25
Chapter 3: Statistical Nano CMOS Variability and Its Impact on SRAM 26
3.1 Introduction 26
3.2 Process Variability Classification 28
3.3 Sources of Statistical Variability 30
3.4 Statistical Aspects of Reliability 31
3.5 Gate Leakage Variability 35
3.6 Simulation of Statistical Variability 36
3.7 Simulation of Statistical Reliability 39
3.8 Variability in Future Technology Generations 42
3.9 Compact Model Strategies for Statistical Variability 47
3.10 Basics of Statistical Circuit Simulations in the Presence of Statistical Variability 51
3.11 Conclusions 55
References 56
Chapter 4: Importance Sampling-Based Estimation: Applications to Memory Design 59
4.1 Introduction 59
4.2 Statistical Sampling 60
4.2.1 Probability and Statistics: A History in the Making 60
4.2.2 Overview of Sampling Methods 60
4.2.3 Random Sample Generation 61
4.2.3.1 Pseudo-Random Number Generation 61
4.2.3.2 Generating Normally Distributed Random Numbers 62
4.2.3.3 Box-Muller Approach 63
4.2.3.4 Ziggurat Method 64
4.2.3.5 Generating Samples from Multi-Variate Gaussian Distributions 65
4.2.3.6 Correlated Gaussian Random Variables 66
4.3 Monte Carlo Methods 67
4.3.1 The Beginning 68
4.3.2 Numerical Integration 68
4.3.2.1 Deterministic Methods 68
4.3.2.2 Curse of Dimensionality and Need for Monte Carlo Integration 70
4.3.2.3 Latin Hypercube Sampling 71
4.3.3 Statistical Inference 71
4.3.3.1 Mean and Variance 72
4.3.3.2 Confidence Intervals 74
4.3.3.3 Statistical Inference for Proportions (Probabilities) 75
4.3.3.4 Statistical Inference for Frequencies 77
4.3.3.5 Reliability Engineering and Monte Carlo: Acceptance Space Complexity 79
4.3.3.6 Resampling: Cross-Validation and Bootstrapping 80
4.3.4 Rare Event Estimation and Monte Carlo 82
4.4 Variance Reduction and Importance Sampling 84
4.4.1 An Overview of Variance Reduction Methods 84
4.4.1.1 Control Variates 84
4.4.1.2 Antithetic Variates 85
4.4.1.3 Quasi-Monte Carlo Methods 85
4.4.1.4 Stratified Sampling 88
4.4.2 Importance Sampling 88
4.4.2.1 Integrated Importance Sampling 90
4.4.2.2 Ratio and Regression Estimates 91
4.4.2.3 Variance and Confidence Intervals 91
4.4.2.4 Exponential Change of Measure 92
4.5 Importance Sampling for Memory Design 92
4.5.1 The Importance Sampling Distribution 92
4.5.1.1 Shifted Mean Estimation 94
4.5.1.2 Theoretical Application 95
4.5.2 SRAM Application 97
4.5.2.1 Dynamic Stability and Writability for PD/SOI Designs 98
4.5.2.2 Yield Analysis 98
4.5.2.3 Effects of Supply Fluctuation 100
4.6 Conclusions 102
References 103
Chapter 5: Direct SRAM Operation Margin Computation with Random Skews of Device Characteristics 105
5.1 Introduction 105
5.2 General Metrics for SRAM Operation Margins 106
5.3 Idealization of Statistical Chaos in Single Variable 109
5.4 Formulation of the Direct Computation for SRAM Margins 110
5.5 Example ADM and WRM Computation 115
5.6 Extending DC Computation to Transient Operations 118
5.7 Unstable SRAM Cells at High Vdd and High Beta Ratio 121
5.8 Write Fail from New Floating Bodies 124
5.9 General Transient Margin Computation Sequence and DC Margin Bias Setting 125
5.10 Thinner Tinv to Mitigate Floating Body Effects Which Degrade SRAM Stability 127
5.11 SRAM Wear and Tear from NBTI and PBTI 128
5.12 SRAM Vmax Problem from DIBL 133
5.13 Getting Around Curvatures of Metric Gradients 135
5.14 Conclusion and Acknowledgment 141
Appendix: SRAM Margins to Meet Yield Targets 143
References 143
Chapter 6: Yield Estimation by Computing Probabilistic Hypervolumes 145
6.1 Introduction: Parameter Variations and Yield Estimation 145
6.1.1 Yield Estimation 147
6.1.2 An Example: SRAM Read Access Failure 149
6.2 Approaches to Yield Estimation 151
6.2.1 Statistical Methods 152
6.2.1.1 Monte-Carlo Methods 152
6.2.1.2 Improved Monte-Carlo Methods 154
6.2.2 Deterministic/Mixed Methods 154
6.2.2.1 Yield Estimation by Simplicial Approximation 155
6.2.2.2 Yield Estimation by Worst-Case Distance Approximation 156
6.2.2.3 Yield Estimation by Ellipsoidal Approximation 158
6.2.2.4 Yield Estimation by Euler-Newton Curve Tracing 159
6.2.2.5 YENSS Sampling 160
6.2.2.6 Normal Boundary Intersection: The Reverse Problem 161
6.3 Computing the Boundary and Probabilistic Hypervolumes 162
6.3.1 Basic Idea and Geometrical Explanation 162
6.3.1.1 Extension to Multiple Parameters 162
6.3.1.2 Extension to Multiple Constraints 163
6.3.1.3 Extension to Handling Probability Distributions 163
6.3.1.4 Extension to Handling Correlations of Parameters 166
6.3.2 YENSS Algorithm Outline 168
6.3.3 Implicit Formulation for the Boundary 170
6.3.3.1 SRAM Read Access Time 170
6.3.3.2 SRAM Static Noise Margin while Holding Data 171
6.3.4 Solving for the Boundary Using Line Search 171
6.3.4.1 Dealing with Multiple Performance Constraints 175
6.3.5 Solving for the Boundary Using Moore-Penrose Pseudo-Inverse Newton-Raphson 176
6.3.6 Calculating the Jacobian Matrix Using Sensitivity Analysis 176
6.3.6.1 Transient Simulation Based Sensitivity Evaluation 177
6.3.7 Adaptive Hypervolume Refinement and Error Estimation 178
6.3.7.1 Analytical Formula to Compute the Hypervolume 178
6.3.7.2 Yield Hypervolume Calculation and Error Control 178
6.4 Examples and Comparisons 179
6.4.1 An Illustrative Example of YENSS 179
6.4.2 Application to SRAM Read Access Failure 180
6.5 Summary 182
References 183
Chapter 7: Most Probable Point-Based Methods 186
7.1 Introduction 186
7.2 Linear Limit-State Functions with Normally Distributed Random Variables 188
7.3 First Order Reliability Method 191
7.4 Second-Order Reliability Method 200
7.5 Other Topics of the MPP-Based Methods 205
7.5.1 Dependent Random Variables 205
7.5.2 MPP-Based Monte Carlo Simulation 205
7.5.3 MPP-Based Methods in the Original X-Space 206
7.6 Conclusions 207
References 208
Chapter 8: Extreme Value Theory: Application to Memory Statistics 210
8.1 Introduction 210
8.1.1 Design Margin and Memory 210
8.2 Extremes: Tails and Maxima 214
8.2.1 Sample Maximum: Limiting Distributions 215
8.2.2 Distribution Tail: Limiting Distributions 217
8.3 Analysis of Tails and Extreme Values 218
8.3.1 Order Statistics and Quantiles 218
8.3.1.1 Order Statistics 218
8.3.1.2 Quantiles 219
8.3.2 Mean Excess Plot 220
8.4 Estimating the Tail: Fitting the GPD to Data 221
8.4.1 Maximum Likelihood Estimation 222
8.4.2 Probability-Weighted Moment Matching 223
8.5 Statistical Blockade: Sampling Rare Events 225
8.5.1 Unbiasing the Classifier 227
8.5.2 Note on Sampling and Commercially Available Device Models 228
8.5.3 Example: 6T SRAM Cell 228
8.5.4 Conditionals and Disjoint Tail Regions 231
8.5.4.1 The Solution 232
8.5.5 Extremely Rare Events and Their Statistics 234
8.5.6 A Recursive Formulation of Statistical Blockade 235
8.5.6.1 An Experiment with Data Retention Voltage 236
8.6 Combining Effects Across a Memory 239
8.6.1 Subsystem Results: Bit Cells Connected to a Given Sense Amplifier 239
8.6.2 Generalizing to a Full Memory 241
8.6.2.1 Method 1 (Isolated) 242
8.6.2.2 Method 2 (Merged) 242
8.6.3 Generalization to Multiple Memories 245
8.7 Conclusions 245
References 246
Index 248

Erscheint lt. Verlag 9.9.2010
Reihe/Serie Integrated Circuits and Systems
Zusatzinfo X, 246 p.
Verlagsort New York
Sprache englisch
Themenwelt Technik Elektrotechnik / Energietechnik
Technik Nachrichtentechnik
Schlagworte CMOS • design automation • Device Variability Modeling • Electronic Design Automation • EVT • extreme value theory • Integrated circuit • Material • Memory Design • Nanoscale VLSI • Sampling-Based Estimation • VLSI
ISBN-10 1-4419-6606-4 / 1441966064
ISBN-13 978-1-4419-6606-3 / 9781441966063
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