Power-Aware Computer Systems
Springer Berlin (Verlag)
978-3-540-42329-4 (ISBN)
Power-Aware Microarchitectural/Circuit Techniques.- System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors.- Ramp Up/Down Functional Unit to Reduce Step Power.- An Adaptive Issue Queue for Reduced Power at High Performance.- Application/Compiler Optimizations.- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.- Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering.- Compiler-Directed Dynamic Frequency and Voltage Scheduling.- Exploiting IPC/Memory Slack.- Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power.- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.- Power/Performance Models and Tools.- TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator.- Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.- A Comparison of Two Architectural Power Models.
Erscheint lt. Verlag | 11.7.2001 |
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Reihe/Serie | Lecture Notes in Computer Science |
Zusatzinfo | X, 158 p. |
Verlagsort | Berlin |
Sprache | englisch |
Maße | 155 x 235 mm |
Gewicht | 245 g |
Themenwelt | Mathematik / Informatik ► Informatik |
Technik ► Elektrotechnik / Energietechnik | |
Schlagworte | Compiler • Computer • Energy Dissipation • Hardcover, Softcover / Informatik, EDV/Informatik • HC/Informatik, EDV/Informatik • Low-Power Devices • Modeling • Optimization • Power-Aware Computer Systems • Power-Aware Computing • Power Dissipation • Power-Performance Analysis • Tools |
ISBN-10 | 3-540-42329-X / 354042329X |
ISBN-13 | 978-3-540-42329-4 / 9783540423294 |
Zustand | Neuware |
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