Handbook of Digital Techniques for High-Speed Design - Tom Granberg

Handbook of Digital Techniques for High-Speed Design

Design Examples, Signaling and Memory Technologies, Fiber Optics, Modeling, and Simulation to Ensure Signal In

(Autor)

Buch | Softcover
976 Seiten
2014
Prentice Hall (Verlag)
978-0-13-376474-1 (ISBN)
114,40 inkl. MwSt
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TOM GRANBERG has earned several technical degrees-a B.S. in Physics from Washington State University and an M.S. and Ph.D. in Electrical Engineering from the University of Missouri-Columbia. He also holds an M.B.A. from the University of Colorado at Denver. Tom has worked for dominant networking companies Cisco Systems and SkyStream Networks and in ASIC design emulation at Quickturn Design Systems (a Cadence Company). He has also worked in digital signal processing, digital imaging systems, and flat panel sensors, and at companies including Condor Systems, Martin Marietta (now Lockheed Martin), Storage Technology, and Honeywell Test Instruments. He lives in Santa Clara, California-the heart of the Silicon Valley-and enjoys access to many of the world 's newest technologies.

Preface.

I. INTRODUCTION.

 1. Trends in High-Speed Design.




 2. ASICs, Backplane Configurations, and SerDes Technology.




 3. A Few Basics on Signal Integrity.


II. SIGNALING TECHNOLOGIES AND DEVICES.

 4. Gunning Transceiver Logic (GTL, GTLP, GTL+, AGTL+).
 5. Low Voltage Differential Signaling (LVDS).
 6. Bus LVDS (BLVDS), LVDS Multipoint (LVDM), and Multipoint LVDS (M-LVDS).
 7. High-Speed Transceiver Logic (HSTL) and Stub-Series Terminated Logic (SSTL).
 8. Emitter Coupled Logic (ECL, PECL, LVPECL, ECLinPS Lite and Plus, SiGe, ECL Pro, GigaPro and GigaComm).
 9. Current-Mode Logic (CML).
10. FPGAs - 3.125 Gbps RocketIOs and HardCopy Devices.
11. Fiber-Optic Components.
12. High-Speed Interconnects and Cabling.
III. HIGH-SPEED MEMORY AND MEMORY INTERFACES.

13. Memory Device Overview and Memory Signaling Technologies.
14. Double Data Rate SDRAM (DDR, DDR2) and SPICE Simulation.
15. GDDR3, ZBT, FCRAM, SigmaRAM, RLDRAM, DDR SRAM, Flash, FeRAM, and MRAM.
16. Quad Data Rate (QDR, QDRII) SRAM.
17. Direct Rambus DRAM (DRDRAM).
18. Xtreme Data Rate (XDR) DRAM, FlexPhase and ODR.
IV. MODELING, SIMULATION, AND EDA TOOLS.

19. Differential and Mixed-Mode SParameters.
20. Time Domain Reflectometry (TDR), Time Domain Transmission (TDT), and VNAs.
21. Modeling with IBIS.
22. Mentor Graphics - EDA Tools for High-Speed Design, Simulation, Verification, and Layout.
V. DESIGN CONCEPTS AND EXAMPLES.

23. Advances in Design, Modeling, Simulation, and Measurement Validation of High-Performance Board-to-Board 5-to-10 Gbps Interconnects.
Appendix 23A. Generalized N-Port, Mixed-Mode S-Parameters.
24. IBIS Modeling and Simulation of High-Speed Fiber-Optic Transceivers.
25. Designing with LVDS.
26. Designing to 10 Gbps Using SerDes Transceivers, Serializers, and Deserializers.
27. WarpLink SerDes System Design Example.
VI. EMERGING PROTOCOLS AND TECHNOLOGIES.

28. Electrical Optical Circuit Board (EOCB).
29. RapidIO.
30. PCI Express and ExpressCard.
VII. LAB AND TEST INSTRUMENTATION.

31. Electrical and Optical Test Equipment.
Acronyms.
References.
About the Author.

Erscheint lt. Verlag 20.2.2014
Verlagsort Upper Saddle River
Sprache englisch
Maße 178 x 235 mm
Gewicht 1588 g
Themenwelt Technik Elektrotechnik / Energietechnik
Technik Nachrichtentechnik
ISBN-10 0-13-376474-5 / 0133764745
ISBN-13 978-0-13-376474-1 / 9780133764741
Zustand Neuware
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