Verilog Coding for Logic Synthesis

WENG FOOK LEE is a prominent member of the Technical Staff (MTS) at Advanced Micro Devices (AMD) Design Center. He has vast experience in designing with Verilog and VHDL, and is an acknowledged expert in the field of RTL coding and logic synthesis. Lee is an expert at synthesizing and tweaking design synthesis, and in developing and implementing new logic verification, synthesis, auto-place-route, and back-annotation design methodology. He has experience in the design and synthesis of PCI, ISA and LPC bridges, chipsets, microcontrollers, RISC microprocessors, and state-of-the-art, high-speed, low-power flash memory.

Table of Figures. Table of Examples.

List of Tables.

Preface.

Acknowledgments.

Trademarks.

Introduction.

Asic Design Flow.

Verilog Coding.

Coding Style: Best-Known Method for Synthesis.

Design Example of Programmable Timer.

Design Example of Programmable Logic Block for Peripheral Interface.