Verilog Coding for Logic Synthesis

Verilog is a Hardware Description Language (HDL), used to design and document electronic systems. This book provides a practical approach to Verilog design and problem solving. It includes design examples that include specification, architectural definition and micro-architectural definition. It is useful as a textbook in EE departments.

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This book provides a practical approach to Verilog design and problem solving. The bulk of the book deals with practical design problems that design engineers solve on a daily basis. It includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. The book is suitable for use as a textbook in EE departments that have VLSI courses.